Record Extrinsic Transconductance (2.45 mS/μm at
VDS = 0.5 V) InAs/In0.53Ga0.47As Channel MOSFETs
Using MOCVD Source-Drain Regrowth
Sanghoon Lee1*, C.-Y. Huang1, A. D. Carter1, D. C. Elias1, J. J. M. Law1, V.
Chobpattana2, S. Krӓmer2, B. J. Thibeault1, W. Mitchell1, S. Stemmer2, A. C. Gossard2,
and M. J. W. Rodwell1
1ECE
and 2Materials Departments
University of California, Santa Barbara, CA
2013 Symposium on VLSI Technology
Kyoto, Japan
06/13/2013
*sanghoon_lee@ece.ucsb.edu
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VLSI 2013
Outline
 Motivation: Why III-V MOSFETs?
 Design Considerations
 Process Flow
 Key Process Developments
- Damaged Surface removal
- Interfacial trap Passivation
 Measurement Results
- I-V Characteristics
- Gate leakage & TLM measurement
- Peak gm and Ron VS Lg (Benchmarking)
 Conclusion
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VLSI 2013
Why III-V MOSFETs in VLSI ?
more transconductance per gate width
more current (at a fixed Vdd )→ IC speed
or reduced Vdd (at a constant Ion)→ reduced power
or reduced FET widths→ reduced IC size
increased transconductance from:
low mass→ high injection velocities
lower density of states→ less scattering
higher mobility in N+ regions → lower access resistance
Other advantages
heterojunctions→ strong carrier confinement
wide range of available materials
epitaxial growth→ atomic layer control
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VLSI 2013
Key Design Considerations
Device structure:
Scalability (sub 20 nm-Lg ,<30 nm contact pitch) : self-aligned S/D, very low ρc
Carrier supply: heavily doped N+ source region
Shallow junction: regrown S/D or Trench-gate
Channel Design:
Thinner wavefunction depth: Thin channel
More injection velocity: higher In-content channel
Gate Dielectric:
Thinner EOT : scaled high-k dielectric
Low Dit : surface passivation, minimized process damage
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VLSI 2013
Process Flow
HSQ
HSQ
3/5/3 nm In0.53GaAs/InAs/In0.53GaAs
(Channel)
5 nm n+ InGaAs (Capping layer)
(Regrown S/D)
N+ InGaAs
5 nm n+ InGaAs (Capping layer)
3/5/3 nm Composite Channel
3/5/3 nm Composite channel
InAlAs (Barrier)
InAlAs (Barrier)
InAlAs (Barrier)
InP (Substrate)
InP (Substrate)
5 nm n+ InGaAs (Capping layer)
3 nm 3.9e12/cm2 Pulse doping
InP (Substrate)
- Epitaxial layer growth
using MBE
- Dummy gate definition
using e-beam lithography
- N+ InGaAs S/D regrowth
using MOCVD
3.6 nm HfO2
Ti/Pd/
Au
Ni/Au
N+ InGaAs
(Regrown S/D)
Capping layer
N+ InGaAs
(Regrown S/D)
Capping layer
S/D
metal
Ni/Au
N+ InGaAs
(Regrown S/D)
Capping layer
5/3 nm InAs/InGaAs channel
5/3 nm InAs/InGaAs channel
InAlAs (Barrier)
InAlAs (Barrier)
InAlAs (Barrier)
InP (Substrate)
InP (Substrate)
InP (Substrate)
5/3 nm InAs/InGaAs channel
- Dummy gate removal
- Capping layer digital etching
- High-k deposition
- Post Deposition Annealing
- Gate metal deposition
5
- S/D metal deposition
VLSI 2013
Evidence of Surface Damage During Regrowth
Long-channel FETs: consistently show >100 mV/dec. subthreshold swing
Indicates high Dit despite good MOSCAP data. Suggests process damage.
Experiment: SiO2 capping + high temp anneal + strip  MOSCAP Process
Finding: large degradation in MOSCAP dispersion.
Confirms process damage hypothesis.
o
SiO Capped, 500 C anneal
Control
2
1.2
1 KHz
10 KHz
100 KHz
1 MHz
Capacitance (F/cm2)
1
Large
dispersion
 Large Dit
0.8
0.6
0.4
0.2
0
-2
-1
0
1
2
-2
-1
Voltage (V)
6
0
1
Voltage (V)
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VLSI 2013
2
)
Post-Regrowth Surface Digital Etching for Damage Removal
Damaged surface
HSQ
N+ InGaAs
(Regrown S/D)
N+ InGaAs
5 nm n+ InGaAs (Capping layer)
(Regrown S/D)
Capping layer
3/5/3 nm Composite channel
5/3 nm InAs/InGaAs channel
InAlAs (Barrier)
InAlAs (Barrier)
InP (Substrate)
InP (Substrate)
- Surface removed by digital etch process
# cycles: 15’ UV ozone (surface oxidation)
1’ dilute HCl (native oxide removal)
 13 - 15 Ȧ/cycle, ~0.16 nm RMS roughness
Ti/Pd/
Au
Ni/Au
S/D
metal
(Regrown S/D)swing and transconductance
N+ InGaAs
- Etch significantly
improves
Capping layer
5/3 nm
InAs/InGaAs channel
- Using this
technique,
the upper cladding of the composite channel is
removed
InAlAs (Barrier)
InP (Substrate)
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VLSI 2013
Dit Passivation : In-situ N2 plasma and TMA pretreatment
“False inversion”
- Cyclic H2 plasma
and TMA treatment
 Dit passivated
(A. Carter et al., APEX 2012)
H2+TMA+H2
N2+TMA+N2
- Lower Midgap Dit for
N2 plasma pretreatment
- Al2O3 interfacial layer
is not needed
(V. Chobpattana, et al. APL 2013)
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VLSI 2013
Cross-sectional STEM image
Ni
3.6 nm HfO2
60 nm
5 nm InAs
3 nm In0.53GaAs
Lg ~40 nm
In0.52AlAs
8 nm channel (5 nm/3 nm InAs/In0.53GaAs) ; The InAs channel is not relaxed
~ 3.5 nm HfO2 and ~0.5 nm interfacial layer formed by cyclic N2 and TMA treatment
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VLSI 2013
I-V characteristics for short and long channel devices
1.6
1.4
2.4
2.0
1.2
1.0
1.6
0.8
1.2
0.6
0.8
0.4
0.2
0.0
VDS = 0.5 V
-0.2
0.0
0.2
0.4
0.6
0.4
0.0
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
VDS=0.5 V
VDS=0.05 V
40 nm
70 nm
90 nm
-0.2
2.0
VDS=0.5 V
2.0
1.6
1.6
1.2
1.2
0.8
0.8
0.4
0.4
0.0
-0.2
0.0
0.2
0.4
Gate Bias (V)
0.6
0.0
Current Density (mA/m)
2.4
Gm (mS/m)
Current Density (mA/m)
W = 10.1 μm , L = 510 nm
VDS=0.05 V
0.2
0.4
0.6
Gate Bias (V)
Gate Bias (V)
2.4
0.0
Current Density (mA/m)
40 nm
70 nm
90 nm
10
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
VDS=0.05 V
VDS=0.5 V
SS ~ 93 mV/dec
at VDS=0.05 V
-0.2
0.0
0.2
0.4
Gate Bias (V)
2.2
2.0 VGS = -0.4 V to 1.4 V
1.8
0.2 V increment
1.6 R = 214 Ohm-m
on
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.1
0.2
0.3
0.4
0.6
0.8
0.7
0.6
0.5
VGS = -0.4 V to 1.4 V
0.2 V increment
Ron = 495 Ohm-m
0.4
0.3
0.2
0.1
0.0
0.0
0.1
0.2
0.3
0.4
0.5
Drain Bias (V)
~2.45 mS/μm Peak Gm at VDS=0.5 V , 93 mV/dec long-channel SS
10
0.5
Drain Bias (V)
Current Density (mA/m)
2.8
Current Density (mA/m)
1.8
Gm (mS/m)
Current Density (mA/m)
W = 10.1 μm , L = 40 nm / 70 nm / 90 nm
VLSI 2013
Gate leakage (A/cm )
Gate leakage, access resistance, gm uniformity
Resistance (Ohm-m)
2
800
700
Ti/Pd/Au
Gap
60 nm n++ InGaAs
(regrown contact layer)
600
5 nm n++ InGaAs (Capping layer)
500
Y = 21.8 + 25.1X
400
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
VDS=0.5 V
VDS=0.05 V
-0.2
0.0
0.2
0.4
0.6
Gate Bias (V)
VDS=
~1.2 μm
300
200
Ti/Pd/Au
Gate
metal
50 nm n++ InGaAs
(regrown)
100
5 nm n++ InGaAs
0
0
5
10
3/4/3 nm In0.53GaAs/InAs/In0.53GaAs
15
20
Gap (400
m)
nm In
0.52AlAs
25
(UID) 3 nm 3.9e12/cm2
Pulse doping
Rsheet = 25 ohm/sq ρc= ~4.7 ohm-μm2 ;S.I.
~82
InPOhm-μm RSD : ~8% degradation
gate leakage <10-4 A/cm2 at all bias conditions
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VLSI 2013
Peak gm and Ron vs. Lg (Benchmarking)
2.8
800
Ron (Ohm-m)
Gm_max (mS/m)
2.4
600
2.0
1.6
at Vds=0.5V
D.-H. Kim
2011 IEDM
(HEMT)
D.-H. Kim
2012 IEDM
J.J. Gu
2012 IEDM
1.2
T.-W. Kim
2012 VLSI
Intel
2009 IEDM
This work
400
M. Egard
2011 IEDM
200
Intel
2009 IEDM
D.-H. Kim
2012 IEDM
T.-W Kim
2012 IEDM
Y. Yonai
2011 IEDM
This work
M. Egard
2011 IEDM
0.1
Y. Yonai
2011 IEDM
D.-H. Kim
2012 IEDM
(VDS=1V)
0.8
1
Gate length (m)
0.4
0.01
0.1
Gate length (m)
1
Record Gm over all the gate lengths
Very Low Ron when considering not fully self-aligned S/D contact
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VLSI 2013
Conclusion
 Using digital etching, damaged surface during S/D regrowth
can be effectively removed and the channel thinned in a
nanometer precision without etch-stop.
 Employing N2 plasma and TMA in-situ treatment, thin HfO2
(3.5 nm) gate dielectric can be incorporated with low Dit.
 Peak gm = 2.45 mS/μm at Vds=0.5 V for a 40 nm-Lg device
 Regrown S/D provides very low access resistance (~ 200
ohm-μm) even with non-self aligned S/D metal contact.
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VLSI 2013
Acknowledgment
Thanks for your attention!
Questions?
This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006).
A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and
MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.
*sanghoon_lee@ece.ucsb.edu
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VLSI 2013