Comparison of Ultra-Thin InAs and
InGaAs Quantum Wells and
Ultra-Thin-Body Surface-Channel
MOSFETs
Cheng-Ying Huang1, Sanghoon Lee1, Evan Wilson3, Pengyu Long3,
Michael Povolotskyi3, Varistha Chobpattana2, Susanne Stemmer2,
Arthur Gossard1,2, Gerhard Klimeck3, and Mark Rodwell1
1ECE,
University of California, Santa Barbara
2Materials Department, University of California, Santa Barbara
3Network for Computational Nanotechnology, Purdue University, West
Lafayette, IN
CSW/IPRM 2015
Santa Barbara, CA
Why III-V FETs? Why Ultra-thin channel?
• III-V channel: low electron effective mass high velocity, high
mobility higher current at lower VDD reducing switching power
• Channel thickness (Tch) must be scaled in proportional to gate length (Lg)
to maintain electrostatic integrity.
• For ultra-thin body (UTB) MOSFETs Tch~1/4 Lg, and for FinFETs Tch~1/2 Lg.
• At 7 or 5 nm nodes, channel thickness should be around 2-4 nm.
• Goal: Carefully examine InGaAs and InAs channels. The best design??
300K
Si
InAs
InGaAs
m e*
0.19
0.023
0.041
(cm2/V·s)
1450
33000
12000
μh(cm2/V·s)
370
450
<300
Eg(eV)
1.12
0.354
0.75
εr
11.7
15.2
13.9
a(Å)
5.43
6.0583
(InP)
μe
Quantum confinement effects!!
tSi~5nm
STM-Leti-IBM
14nm UTBSOI
WFIN~8nm
Intel 14nm FinFET
IEDM2014
Makr Bohr, IDF2014
2
Ultra-thin channel 2DEG: Hall results
• Quantum well (QW) 2DEGs were
grown by solid source MBE.
• For wide wells: μInAs > μInGaAs
2
Mobility (cm /Vs)
10000
InAs channel
InGaAs channel
8000
6000
4000
2000
0
0
1
2
3
4
5
6
7
Well Thickness (nm)
8
Carrier concentration(1012cm
-2
• Carrier concentration decreases
due to increased E0.
)
• For narrow wells (~2 nm):
μInAs ≈ μInGaAs
2.2
2.0
1.8
1.6
1.4
1.2
InAs channel
InGaAs channel
0
1
2
3
4
5
6
7
Well Thickness (nm)
8
3
What happens in thin wells?
• Mobility is limited by interface roughness scattering. Strained
InAs growth (S-K mode) might induce higher interface roughness.
2
Mobility (cm V s
-1 -1
)
10
10
7
6
InGaAs
well
interface roughness
remote impurity
10
5
10
4
10
3
10
acoustic phonon
alloy
polar optical phonon
total
µ ~Tch-6
300K
2
5
10
15
20
Well thickness(nm)
C. Y. Huang et al., J. Appl. Phys. 115, 123711 (2013)
In-plane effective mass, m// (m0)
• Electron effective mass are similar for ~2-3 nm InAs and InGaAs
wells because of non-parabolic band effects.
0.10
InGaAs/InP, Nag1993
InAs/InP, Nag1993
InGaAs/InP, Wetzel1992
InGaAs/InP, Hrivnak1992
InAs, Mugny2015
Schneider1995
Wiesner1994
Wetzel1996
0.09
0.08
0.07
0.06
0.05
0.04
InGaAs
0.03
0.02
InAs
0
5
10
15
20
Well Thickness (nm)
J. Appl. Phys. 77, 2828 (1995), Phys. Rev. B, 52, 1038 (1996),
Appl. Phys. Lett 64, 2520 (1994), Appl. Phys. Lett 62, 2416 (1993),
G. Mugny et al., EUROSOI-ULSI conference 2015.
4
Ultra-thin body III-V FETs: Lg~40 nm
1
10
VDS = 0.1 to 0.7 V
0
10
-1
ID (mA/m)
0.2 V increment
2.0
0.2 V increment
InAs
InGaAs
1.6
gm (mS/m)
10
-2
10
-3
10
2.4
VDS = 0.1 to 0.7 V
-4
1.2
10
-5
10
-6
10
-7
10
0.8
0.4
-8
10
-9
10
-0.2 0.0 0.2 0.4 0.6 -0.2 0.0 0.2 0.4 0.6
• UTB FETs with 3 nm channels
were fabricated to compare
InAs and InGaAs channels.
• 1.6:1 Ion and transcoaductance
for InAs channels.
• 10:1 lower Ioff for InGaAs
channels.
ID (mA/m)
1.5
VGS (V)
0.0
VGS (V)
VGS = -0.2 V to 1.0 V VGS = -0.2 V to 1.0 V
0.2 V increment
0.2 V increment
Ron = 292 Ohm-m R = 400 Ohm-m
on
1.0 at VGS = 1.0 V
at V = 1.0 V
GS
InAs
InGaAs
0.5
0.0
0.0
0.2
V
0.4
(V)
0.6
0.2
V
0.4
(V)
0.6
5
On-state performance
VDS = 0.5 V
Ioff = 100 nA/m
300
200
100
100
Gate length (nm)
1000
3 nm InAs
3 nm InGaAs
2.0
Peak gm (mS/m)
Ion (A/m)
400
0
2.4
3 nm InAs
3 nm InGaAs
1000
VGS = 1 V
750
1.6
Ron(Ohmm)
500
1.2
0.8
0.4
0.0
VDS = 0.5 V
0.1
1
Gate length (m)
500
250
3 nm InAs
3 nm InGaAs
RS/D~ 19020 Ohmm
0
0.0
0.1
0.2
Gate length (m)
• Higher Ion and higher gm for UTB InAs FETs than InGaAs UTB FETs.
• InAs FETs achieve gm=2 mS/μm, and Ion=400 μA/μm at VDS=0.5V
and Ioff=100 nA/μm.
• Similar source/drain resistance (RS/D ) ensures that the
performance degradation of InGaAs is not from source/drain, but
from channel itself (slope).
6
150
VDS=0.1 V,3 nm InAs
VDS=0.5 V,3 nm InAs
VDS=0.1 V,3 nm InGaAs
100
VDS=0.5 V,3 nm InGaAs
80
100
3 nm InAs
3 nm InGaAs
Vth at 1 A/m
50
IOFF, MIN (nA/m)
120
DIBL (mV/V)
Subthreshold Swing (mV/dec)
Subthreshold swing and off-state current
10
2
10
1
10
0
10
-1
10
-2
3 nm InAs
3 nm InGaAs
VDS = 0.5 V
60
0.1
1
Gate Length (m)
0
0.1
1
10
-3
Gate length (m)
100
1000
Gate length (nm)
• Superior SS~83 mV/dec. and DIBL~110 mV/V because of ultra-thin
channels and improved electrostatics.
• Minimum Ioff is 10:1 lower for InGaAs channel at short Lg, where
leakage current limited by band-to-band tunneling.
• InGaAs FETs are limited by gate leakage at long Lg.
7
Why QW-2DEGs and UTB-FETs show different results?
• 1st possible cause: Electron population in L valley due to strong
quantum confinement  Unlikely.
2nm InAlAs barrier,
3nm InGaAs channel
with H passivation
on top
Courtesy of Evan
Wilson, Pengyu
Long, Michael
Povolotskyi, and
Gerhard Klimeck.
2nm InAlAs barrier,
3nm InAs channel
with H passivation
on top
In0.53Ga0.47As
InAs
me* at Γ [m0]
0.080
0.063
Γ – L separation [eV]
0.596
0.905
Eg at Γ [eV]
1.06
0.639
8
Why QW-2DEGs and UTB-FETs show different results?
• 2nd possible cause: Electron interaction with oxide traps inside
conduction band  Likely.
• Electrons in high In% content channels have less scattering and
less electron capture by the oxide traps.
J. Robertson et al., J. Appl. Phys. 117, 112806 (2015)
J. Robertson, Appl. Phys. Lett. 94, 152104 (2009)
N. Taoka et al., Trans. Electron Devices. 13, 456 (2011)
N. Taoka et al., IEEE IEDM 2011, 610.
9
UCSB Lg~12 nm III-V MOSFETs (DRC 2015)
N+InGaAs
N+InP
~ 8nm
Ni
InAlAs
Barrier
tch~ 2.5 nm
(1.5/1 nm InGaAs/InAs)
2.0
1.6
1.2
0.8
0.4
0.0
VGS = -0.2 V to 1.2 V
ID (mA/m)
InP spacer
2.4
gm (mS/m)
Lg~12nm
ID (mA/m)
1
10
0 VDS = 0.1 to 0.7 V, 0.2 V increment
10
SS~107 mV/dec.
-1
10 SS~98 mV/dec.
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-0.2 0.0 0.2 0.4 0.6 0.8
VGS (V)
1.5
1.0
0.2 V increment
Ron = 302 Ohm-m
at VGS = 1.0 V
0.5
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VDS (V)
Ion/Ioff>8.3·105
10
Summary
• Below 10 nm logic nodes, ultrathin channels are required.
• In QW 2DEGs, the electron Hall mobility are similar for
InGaAs and InAs wells as the wells thinned to 2~3nm.
• In UTB MOSFETs, 3 nm InAs channels significantly improve
on-state current and transconductance (~1.6:1), and reduce
channel resistance as compared to 3 nm InGaAs channel.
• Purdue’s tight-binding calculations show large ~0.6 eV Γ–L
splitting in 3 nm InGaAs channels, ruling out the possibility
of electron population in L-valley.
• UCSB C-V measurements show large dispersion in 3 nm
InGaAs channels, possibly indicating the significant electron
interactions with oxide traps. (As-As anti-bonding may be
the culprit)
11
Acknowledgment
Thanks for your attention!
Questions?
• This research was supported by the SRC Non-classical CMOS
Research Center (Task 1437.009) and GLOBALFOUNDRIES(Task
2540.001).
• A portion of this work was done in the UCSB nanofabrication
facility, part of NSF funded NNIN network.
• This work was partially supported by the MRSEC Program of the
National Science Foundation under Award No. DMR 1121053.
cyhuang@ece.ucsb.edu
(backup slides follow)
Mobility in different channel design: 25 µm-Lg
1.5
4
1.0
2
0.5
0.2
0.4
VGS (V)
0.6
0
0.8
)
0.0
-2
0.0
-0.2
1000
800
2
2
1200
Mobility (cm /Vs)
6
Freq.: 200 kHz
W/L=25m/21m
12
Effective CG (F/cm )
4.5 nm InGaAs
2.5 nm InAs
5.0 nm InAs
2.5
2.0
8
Carrier density (10 cm
3.0
4.5 nm InGaAs
2.5 nm InAs
5.0 nm InAs
600
400
200
0
0
1
2
3
4
5
6
-2
Carrier density (cm )
m*, Cg-ch, RS/D more important for ballistic FETs
7