High Transconductance Surface Channel In0.53Ga0.47As
MOSFETs Using MBE Source-Drain Regrowth and
Surface Digital Etching
Sanghoon Lee1*, C.-Y. Huang1, A. D. Carter1, J. J. M. Law1, D. C. Elias1, V.
Chobpattana2, B. J. Thibeault1, W. Mitchell1, S. Stemmer2, A. C. Gossard2, and M. J. W.
Rodwell1
1ECE
and 2Materials Departments
University of California, Santa Barbara, CA
2013 Conference on Indium Phosphide and Related Materials
Kobe, Japan
05/22/2013
*sanghoon_lee@ece.ucsb.edu
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Outline
 Motivation: Why III-V MOSFETs?
 Key Design Considerations
- Device Structure : Gate-last with S/D regrowth
- Damage during regrowth : surface digital etching
 Process Flow
 Measurement Results
- I-V Characteristics
- TLM measurement
 Conclusion
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Why III-V MOSFETs in VLSI ?
more transconductance per gate width
more current (at a fixed Vdd )→ IC speed
or reduced Vdd (at a constant Ion)→ reduced power
or reduced FET widths→ reduced IC size
increased transconductance from:
low mass→ high injection velocities
lower density of states→ less scattering
higher mobility in N+ regions → lower access resistance
Other advantages
heterojunctions→ strong carrier confinement
wide range of available materials
epitaxial growth→ atomic layer control
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Key Design Considerations
Device structure:
Scalability (sub 20 nm-Lg,<30 nm contact pitch) : self-aligned S/D, very low ρc 2)
Carrier supply: heavily doped N+ source region3)
Shallow junction: regrown S/D3) or Trench-gate
Channel Design:
Thinner wavefunction depth: Thin channel, less pulse doping.
More injection velocity: high In-content channel4)
Gate Dielectric:
Thinner EOT : scaled high-k dielectric
Low Dit : surface passivation5), minimized process damage6)
1) M. Wistey et al. EMC 2009; 2) A. Baraskar et al. IPRM 2010 ; 3) U. Singisetti et at. EDL 2009 ;
4) S. Lee et al. EDL 2012 (accepted); 5) A. Carter et at. APEX 2011; 6) G. Burek, et al, JVST 2011.
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Device Structure : Gate-Last process
Gate-First
Fully self-aligned transistor at nm dimensions
Process damage during gate metal deposition and definition
Large ungated region: High pulse doing
 Large leakage current and increase in wavefunction depth
A. Carter et at., DRC 2011
Gate-Last (substitutional-gate)
Low-damage process: Thermal gate metal,
No plasma process after gate dielectric deposition
Rapid turn-around  rapid learning.
Ti/Pd/
Au
S/D
metal
Ni/Au
N+ InAs
(Regrown S/D)
Capping layer
10 nm InGaAs (Channel)
InAlAs (Barrier)
InP (Substrate)
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Evidence of Surface Damage During Regrowth
Long-channel FETs: consistently show >100 mV/dec. subthreshold swing
Indicates high Dit despite good MOSCAP data. Suggests process damage.
Experiment: SiO2 capping + high temp anneal + strip  MOSCAP Process
Finding: large degradation in MOSCAP dispersion.
Confirms process damage hypothesis.
o
SiO Capped, 500 C anneal
Control
2
1.2
1 KHz
10 KHz
100 KHz
1 MHz
Capacitance (F/cm2)
1
Large
dispersion
 Large Dit
0.8
0.6
0.4
0.2
0
-2
-1
0
1
2
-2
-1
Voltage (V)
6
0
1
Voltage (V)
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Post-Regrowth Surface Digital Etching for Damage Removal
HSQ
(Regrown S/D)
N+ InAs
5 nm n+ InGaAs (Capping layer)
N+ InAs
(Regrown S/D)
Capping layer
10 nm InGaAs (Channel)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InAlAs (Barrier)
InP (Substrate)
InP (Substrate)
- Surface removed by digital etch process
2’ in BOE (dummy gate removal) ,
# cycles: 15’ UV ozone (surface oxidation)
1’ dilute HCl (native oxide removal)
 13 - 15 Ȧ/cycle, ~0.16 nm RMS roughness
- Etch significantly improves subthreshold swing and gm
- Using this technique, we can easily thin the channel thickness.
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Process Flow
HSQ
HSQ
5 nm n+ InGaAs (Capping layer)
HSQ
(Regrown S/D)
N+ InAs
5 nm n+ InGaAs (Capping layer)
(Regrown S/D)
N+ InAs
5 nm n+ InGaAs (Capping layer)
10 nm InGaAs (Channel)
10 nm InGaAs (Channel)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InAlAs (Barrier)
InAlAs (Barrier)
InP (Substrate)
InP (Substrate)
InP (Substrate)
- Epitaxial layer growth
- Dummy gate definition
- InAs Source/Drain regrowth
- Mesa isolation
- InAs debris wet-etching
3 nm 3.9e12/cm2 Pulse doping
1 nm/ 4 nm Al2O3/HfO2
Ti/Pd/
Au
Ni/Au
N+ InAs
(Regrown S/D)
Capping layer
N+ InAs
(Regrown S/D)
Capping layer
S/D
metal
Ni/Au
N+ InAs
(Regrown S/D)
Capping layer
10 nm InGaAs (Channel)
10 nm InGaAs (Channel)
10 nm InGaAs (Channel)
InAlAs (Barrier)
InAlAs (Barrier)
InAlAs (Barrier)
InP (Substrate)
InP (Substrate)
InP (Substrate)
- Dummy gate removal
- Capping layer digital etching
- High-k deposition
- Annealing
- Gate metal deposition
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- S/D metal deposition
IPRM 2013
2.0
1.8
1.6
1.4
1.2
1.6
1.4
1.2
1.0
0.8
0.6
0.4
VDS = 0.5 V
VDS = 0.05 V
0.2
0.0
-0.2
0.0
0.2
0.4
0.6
1.0
0.8
0.6
0.4
0.2
0.0
0.8
Current Density (mA/m)
2.0
1.8
Gm (mS/m)
Current Density (mA/m)
I-V Characteristics for short and long channel devices
10
1
10
0
10
-1
10
-2
10
-3
10
-4
VDS = 0.5 V
VDS = 0.05 V
SS ~ 120 mV
at VDS=0.05 V
-5
10
-0.2
0.0
0.6
VDS = 0.1 V to 0.7 V
0.5
0.2 V increment
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
-0.2
0.0
0.2
0.4
0.6
0.8
0.0
1.0
Current Density (mA/m)
0.6
0.5
0.4
0.6
0.8
Gate Bias (V)
Gm (mS/m)
Current Density (mA/m)
Gate Bias (V)
0.2
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
VDS = 0.1 V to 0.7 V
SS ~ 95 mV
at VDS=0.1V
-6
10
-0.2
Gate Bias (V)
0.2 V increment
0.0
0.2
0.4
0.6
0.8
1.0
Gate Bias (V)
- 1.6 mS/μm at Vds=0.5 V for a 65 nm-Lg device.
- 95 mV/dec SS for a 530 nm-Lg device.
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Comparison with a control sample (short channel)
0.2 V increment
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
1.2
1.0
1.2
VDS = 0.1 V to 0.7 V
1.0
0.2 V increment
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
-0.4 -0.2
0.0
0.2
0.4
0.6
0.0
0.8
Current Density (mA/m)
1.2
VGS = -0.4 V to 1.8 V
Current Density (mA/m)
1.4
Gm (mS/m)
Current Density (mA/m)
Control : without capping layer and surface digital etching, 75 nm-Lg
Gate Bias (V)
Drain Bias (V)
10
1
10
0
10
-1
10
-2
10
-3
10
-4
VDS = 0.1 V to 0.7 V
0.2 V increment
SS ~ 258 mV
at VDS=0.1 V
-5
10
-0.4 -0.2
0.2 V increment
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Drain Bias (V)
1.6
1.8
VDS = 0.1 V to 0.7 V
1.4
1.6
0.2 V increment
1.4
1.2
1.2
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
-0.2
0.0
0.2
0.4
Gate Bias (V)
0.6
0.0
0.8
Current Density (mA/m)
VGS = 0 V to 1.6 V
Current Density (mA/m)
1.2
1.8
Gm (mS/m)
Current Density (mA/m)
Experimental : with surface digital etching , 75 nm-Lg
1.4
0.0
0.2
0.4
0.6
0.8
Gate Bias (V)
10
1
10
0
VDS = 0.1 V to 0.7 V
10
-1
10
-2
10
-3
10
-4
0.2 V increment
SS ~ 124 mV
at VDS=0.1V
-5
10
-0.2
0.0
0.2
0.4
0.6
0.8
Gate Bias (V)
- ~75 % increase in peak transconductance at Vds = 0.5 V
- significantly better short channel characteristic with surface digital etching
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Comparison with a control sample (long channel)
0.2 V increment
0.4
0.3
0.2
0.1
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.6
0.5
0.6
VDS = 0.1 V to 0.7 V
0.5
0.2 V increment
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
-0.2
0.0
0.2
0.4
0.6
0.8
0.0
1.0
Current Density (mA/m)
0.5
VGS = -0.4 V to 1.4 V
Current Density (mA/m)
0.6
Gm (mS/m)
Current Density (mA/m)
Control : without surface digital etching, 500 nm-Lg
10
1
10
0
10
-1
10
-2
10
-3
10
-4
VDS = 0.1 V to 0.7 V
0.2 V increment
SS ~ 240 mV
at VDS=0.1 V
-5
10
-0.2
0.0
Gate Bias (V)
Drain Bias (V)
0.3
0.2
0.1
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Drain Bias (V)
0.5
0.6
VDS = 0.1 V to 0.7 V
0.5
0.2 V increment
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
-0.2
0.0
0.2
0.4
0.6
0.8
0.0
1.0
Gate Bias (V)
- Similar on-state characteristics (~0.4 V Vt shift)
- Better short channel effect
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Current Density (mA/m)
0.4
Current Density (mA/m)
0.2 V increment
0.6
Gm (mS/m)
Current Density (mA/m)
0.5
VGS = 0 V to 1.8 V
0.4
0.6
0.8
1.0
Gate Bias (V)
Experimental : with surface digital etching, 535 nm-Lg
0.6
0.2
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
VDS = 0.1 V to 0.7 V
0.2 V increment
SS ~ 95 mV
at VDS=0.1V
-6
10
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Gate Bias (V)
IPRM 2013
TLM Measurement for S/D metal contact
Resistance (Ohm-m)
800
Y = 3.9 + 25.1X
2
600 c = 0.15 -m
500 RSD= 64 -m
700
~1.2 μm
Ti/Pd/Au
400
50 nm n++ InAs
(regrown)
300
5 nm n++ InGaAs
Ti/Pd/Au
200
Gap
InGaAs Channel
50 nm n++ InAs
(regrown contact layer )
100
0
Gate
metal
5 nm n++ InGaAs (Capping layer )
0
5
10
15
Gap (m)
20
25
400 nm In0.52AlAs (UID) 3 nm 3.9
Pulse
S.I. InP
- 0.15 ohm-μm2 Contact resistivity and 25 ohm/sq. sheet resistance.
- 64 ohm-μm S/D access resistance (~5 % transconductance degradation)
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Conclusion
 Using digital etching, damaged surface can be effectively
removed in a nanometer precision without etch-stop.
 The removal of the damaged surface significantly improves
both on- and off-state performance.
 gm = 1.6 mS/μm at Vds=0.5 V for a 65 nm-Lg device
95 mV/dec for a 530 nm-Lg device
 InAs regrown S/D provides very low contact resistivity of
0.15 ohm-μm2 .
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Thanks for your attention!
Questions?
This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006).
A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and
MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.
*sanghoon_lee@ece.ucsb.edu
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