227th Electrochemical Society Meeting, Chicago, May 24-28, 2015
Record-Performance In(Ga)As MOSFETs
Targeting ITRS High-Performance
and Low-Power Logic
M. Rodwell, C. Y. Huang, S. Lee, V. Chobpattana,
B. Thibeault, W. Mitchell, S. Stemmer, A. Gossard
University of California, Santa Barbara
Why III-V MOS ?
III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering
→ higher current. Can then trade for lower voltage or smaller FETs.
Problems: Low m*→ less charge. Low m* → more S/D tunneling.
Narrow bandgap→ more band-band tunneling, impact ionization.
2
InGaAs/InAs FETs are leaky!
Lg = 25 nm
gm (mS/m)
Current Density (mA/m)
3.0
10
I
=
500

A/

m
at
I
=100
nA/

m
on
off
0
10 and V =0.5V
2.5
D
-1
10 SS~ 72 mV/dec.
2.0
-2
10 SS~ 77 mV/dec.
-3
1.5
10
-4
10
1.0
-5
10
0.5
-6
10
-7
10 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.50.0
Gate Bias (V)
Ion (mA/m)
1
0.50
VDS = 0.5 V
0.45
Ioff=100 nA/m
0.40
0.35
0.30
S. Lee, VLSI 2014
J. Lin, IEDM 2013
T. Kim, IEDM 2013
Intel, IEDM 2009
J. Gu, IEDM 2012
D. Kim, IEDM 2012
0.25
0.20
0.15
0.10
10
100
Gate Length (nm)
HP = High Performance: Ioff =100 nA/m
GP = General Purpose: Ioff =1 nA/m
LP = Low Power: Ioff =30 pA/m
ULP = Ultra Low Power: Ioff =10 pA/m
3
Device Structures: Lateral Spacers & Tunneling
Small S/D contact pitch
no lateral gate-drain space
MOS-HEMT with large contact pitch
~70 nm gate-drain space
Lin, IEDM2013
UCSB
4
We must build devices with small S/D pitch.
contact pitch ~ 3 times lithographic half-pitch
(technology node dimension)
Intel 35nm NMOS
Small S/D pitch hard to realize if we require ~20-50nm lateral gate-drain spacers !
5
Reducing leakage (1)
 Wide band-gap barriers or P-doped
back barriers reduces bottom leakage
path.
 Solution 1: AlAsSb barriers (Sample
B) reduces subthreshold leakage.
 Solution 2: P-doped InAlAs barriers
also work well.
Ti/Pd/
Au
Ti/Pd/
Au
Ni/Au
50 nm
N+ InGaAs
50 nm
N+ InGaAs
10 nm InGaAs N.I.D channel
3 nm AlAsSb N.I.D spacer
3 nm Si-doped InAlAs
25 nm AlAsSb N.I.D barrier
375 nm InAlAs N.I.D buffer
Semi-insulating InP substrate
C. Y. Huang et al., APL., 103, 203502 (2013)
6
Reducing leakage (1)
 Wide band-gap barriers or P-doped
back barriers reduces bottom leakage
path.
 Solution 1: AlAsSb barriers (Sample
B) reduces subthreshold leakage.
 Solution 2: P-doped InAlAs barriers
also work well.
Ti/Pd/
Au
Ti/Pd/
Au
Ni/Au
50 nm
N+ InGaAs
50 nm
N+ InGaAs
10 nm InGaAs N.I.D channel
3 nm AlAsSb N.I.D spacer
3 nm Si-doped InAlAs
25 nm AlAsSb N.I.D barrier
375 nm InAlAs N.I.D buffer
Semi-insulating InP substrate
C. Y. Huang et al., APL., 103, 203502 (2013)
7
Reducing leakage (2): Source/Drain Vertical Spacer
Gate
Source
Spacer
Drain
Spacer
Channel
Barrier
Substrate
Spacer
S. Lee et al., APL 103, 233503 (2013)
C. Y. Huang et al., DRC 2014.
Vertical spacers reduce the peak electric field, improve electrostatics,
and reduce BTBT floor.
8
Vertical spacers: some details
Minimum S/D contact pitch:
depends upon regrowth angle
vertical growth reported in literature
our recent results: vertical
Spacer sidewalls are gated through the high-K.
Capacitance to UID sidewalls is small.
added gate length→ adds ~0.3 fF/m.
Capacitance to N+ contacts layers is large.
easy to eliminate: low-er sidewall spacer.
Deliberate band offset between spacer & channel
compensates offset from strong quantization in channel.
9
Reducing leakage (3): Ultra-thin channel
Courtesy of S. Kraemer (UCSB)
*Heavy elements look brighter
Lee et al., 2014 VSLI Symposium
1.2
1.0
VGS = -0.4 V to 0.7 V
Current Density (mA/m)
Current Density (mA/m)
Reducing leakage (3): Ultra-thin channel
0.1 V increment
Ron = 303 Ohm-m
0.8 at V = 0.7 V
GS
0.6
0.4
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Drain Bias (V)
SSmin (mV/dec.)
110
100
90
80
Ion (mA/m)
[2]
[4]
[3]
[7]
[1]
[6]
[5]
Open: VDS = 0.1 V
Gate Length (m)
0
10
Lg = 25 nm
VDS = 0.1 to 0.7 V
0.2 V increment
-2
10
-3
10
-4
DIBL = 76 mV/V
-5
VT = -85 mV at 1 A/m
-6
SSmin~ 72 mV/dec. (at VDS = 0.1 V)
-7
SSmin~ 77 mV/dec. (at VDS = 0.5 V)
10
10
10
10
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
0.50
VDS = 0.5 V
0.45
Ioff=100 nA/m
0.40
0.35
0.30
0.25
0.20
0.10
This work
0.1
10
-1
0.15
70
60
0.01
1
Gate Bias (V)
Solid: VDS = 0.5 V
120
10
S. Lee et al., VLSI 2014
1
10
S. Lee, VLSI 2014
J. Lin, IEDM 2013
T. Kim, IEDM 2013
Intel, IEDM 2009
J. Gu, IEDM 2012
D. Kim, IEDM 2012
100
Gate Length (nm)
[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013
[5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009
11
-2
10
Dot : Reverse Sweep
Solid: Forward Sweep
Lg = 1 m
10
1
10
0
10
-1
10
-2
10
-3
-3
10
-4
10
-5
10
-6
10
-7
10
-8
SSmin~ 61 mV/dec.
(at V
DS
= 0.1 V)
SSmin ~ 63 mV/dec. 10-4
(at V
= 0.5 V)
10
10
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DS
-5
2
Current Density (mA/m)
-1
10
|Gate Leakage| (A/cm )
MOSFET: 2.5nm ZrO2/ 1nm Al2O3 / 2.5nm InAs
Gate Bias (V)
61 mV/dec Subthreshold swing at VDS=0.1 V
Negligible hysteresis
12
Compared to Intel 14nm finFET
S. Natarajan et al, IEDM 2014, December, San Francisco
Ioff=10nA/m, Ion=0.45mA/m @VDS=0.5V per m of fin footprint
Re-normalizing to fin periphery: ~0.24 mA/m
13
Off-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel
2.5 nm InAs
5.0 nm InAs
2.5 nm InAs
100
Open: VDS = 0.1 V
90
Solid: VDS = 0.5 V
80
70
0.1
Gate Length (m)
1
Current Density (mA/m)
SSmin (mV/dec)
110
60
0.01
5.0 nm InAs
0
10
SS ~ 60 mV/dec
-1
10 at V =0.1 V
DS
-2
L
=500
nm
10
g
SS ~ 64 mV/dec
at VDS=0.1 V
Lg =500 nm
-3
10
-4
10
ID
ID
-5
10
-6
10
-7
10
-8
10
IG
IG
-9
10
-10
10
-0.2 0.0
0.2
0.4 -0.2 0.0
Gate Bias (V)
0.2
0.4
Gate Bias (V)
Better SS at all gate lengths
 Better electrostatics (aspect ratio) and reduced BTBT (quantized Eg)
~10:1 reduction in minimum off-state leakage
~5:1 increase in gate leakage  increased eigenstate
14
On-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel
2.8
1200
InAs channel thickness
2.5 nm
5.0 nm
1.2
0.8
400
200
VDS = 0.5 V
0
7
2.0
W/L= 25m/21 m
2
Cox = 4.2 F/cm
6
5
EOT= 0.8 nm
1.5
4
1.0
3
2
0.5
2.5 nm InAs
5.0 nm InAs
0.0
0.2
0.4
Gate Bias (V)
0.6
1
0
Energy (eV)
Freq: 200kHz
Carrier Density (/cm )
Gate Length (m)
0
1
12
0.1
2.5
0.0
-0.2
600
x 10
0.4
800
2
1.6
0.0
0.01
Gate Capacitance (F/cm2)
eff (cm /s-V)
2.0
1000
2
Peak gm (mS/m)
2.4
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
2.5 nm InAs
5.0 nm InAs
1
2
3
4
5
6
Carrier Density (/cm2)
~1.25 nm
EF
E1
2.5 nm thick
10
20
30
Position (nm)
7
12
x 10
~2.5 nm
EF
E1
5 nm thick
10
20
30
Position (nm)
1D-Possion Schrodinger solver
(coded by W. Frensley, UT Dallas)
15
ZrO2 vs. HfO2: Peak gm, SS, split-CV, and mobility
Comparison: two process runs ZrO2 , one run HfO2 , both 2nm (on 1nm Al2O3)
VDS = 0.5 V
1.6
0.8
0425A1 (30A ZrO2)
0425A2 (30A HfO2)
VLSI (30A ZrO2)
0.4
0.1
2.0
1.5
7
W/L= 25m/21 m
6
ZrO2
HfO2
5
4
3
1.0
2
0.5
0.0
1
0.0
0.2
0.4
Gate Bias (V)
0.6
0
2
Freq: 200kHz
Carrier Density (/cm )
x 10
Gate Length (m)
1
SSmin (mV/dec)
1.2
2.5
VLSI (30A ZrO2)
0425A1 (30A ZrO2)
0425A2 (30A HfO2)
85
0.0
0.01
Gate Capacitance (F/cm2)
90
2.0
12
Peak gm (mS/m)
2.4
80
75
70
65
Open: VDS = 0.1 V
60 Solid: V = 0.5 V
DS
0.01
0.1
Gate Length (m)
(1) ZrO2 higher capacitance than HfO2 , (2) ZrO2 results are reproducible
1
16
Reducing leakage (4): Thin InGaAs Channel
Spacer
E2
E2
E1
E1
-4
1.2
10
-5
10
-6
10
-7
10
0.8
VDS = 0.1 V (solid)
-8
10
-9
10
0.4
0.5 V (dash)
-0.2
0.0
0.2
VGS (V)
0.4
0.6
0.0
ID, |IG| (mA/m)
2.0
1.6
Tch
1
2.4
gm (mS/m)
IDS (mA/m)
1
10
0 Sample A: black
10 Sample B: red
-1
10 Lg=22 nm
-2
10
-3
10
10
0 VDS = 0.1 to 0.7 V
10
-1 0.2 V increment
10
Sample B
-2
10 L ~22 nm
g
-3
10
I
-4
10
-5
10
-6
10
-7
10
D
BTBT
limited
|IG|
-8
10
-9
10
-0.4 -0.2 0.0 0.2 0.4 0.6
VGS (V)
Reducing channel thickness improves electrostatics, increases
confinement bandgap and reduces BTBT.
17
InGaAs vs. InAs Channel
Huang: IPRM 2015
similar mobility in 2-3 nm thick quantum well
InGaAs has lower on-current in FET with 3nm thick channel ?!?
18
E-field and BTBT contour
R. Chu et al., EDL 29, 974 (2008)
J. Lin et al., EDL 35, 1203 (2014)
Concentrated electric field at the drain end of the channel
Solution:
Replace InGaAs with wide band-gap InP (Eg~1.35 eV)
19
Reducing leakage (5): Doping-graded InP spacer
C-Y Huang, 2014 IEDM
Ti/Pd/Au
Ni/Au
Ni/Au
50 nm N+InGaAs
50 nm N+InGaAs
10 nm N+InP
10 nm N+InP
8 nm doping-graded InP
8 nm doping graded InP
5 nm U.I.D InP
5 nm U.I.D InP
4.5 nm InGaAs
5 nm InAlAs U.I.D. spacer
2 nm 1E19 cm-3 N+InAlAs
100 nm InAlAs U.I.D. buffer
250 nm 1E17 cm-3 P-InAlAs
50 nm InAlAs U.I.D buffer
3 nm
S.I. InP substrate
Ron at
zero Lg
(Ω∙μm)
5 nm
UID InP
13 nm
UID InP
Doping
graded InP
~199
~364
~270
10
0 VDS = 0.1 to 0.7 V
10
-1 0.2 V increment
10
-2
10
-3
ID
10
-4
10
-5
10
-6
|IG|
10
-7
10
-8
10
-9
10
-0.2
0.0
0.2
2.4
2.0
1.6
gm (mS/m)
ZrO2
Lg-30 nm, 30Å ZrO2
ID, |IG| (mA/m)
Ti/Pd/Au
1
1.2
0.8
0.4
0.4
0.6
0.0
VGS (V)
Doping-graded InP spacer reduces parasitic source/drain
resistance and improves Gm.
Gate leakage limits Ioff~300 pA/μm.
20
Reducing leakage (6): Thicker Dielectric
ID, |IG| (mA/m)
2.0
0.0
VGS (V)
1.6
1.2
-1
0.3
0.6
10
-2
10
-3
10
2.0
0.2 V increment
1.6
-4
0.4
10
-5
10
-6
10
-7
10
0.0
10
-9
10
0.8
2.4
10
= 0.1 to 0.7 V
0 V
DS
10
gm (mS/m)
-0.6 -0.3
1
2.4
gm (mS/m)
10
= 0.1 to 0.7 V
0 V
10 DS
-1 0.2 V increment
10
-2
10 38Å ZrO2
-3
10
ID
-4
10
-5
10 60 pA/μm
-6
10
-7
10
|IG|
-8
10
-9
10
InGaAs spacer
ID (mA/m)
1
InP graded spacer
1.2
0.8
0.4
-8
-0.2
0.0
0.2
0.4
0.6
0.0
VGS (V)
Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm
100:1 smaller Ioff compared to InGaAs spacer
C-Y Huang, 2014 IEDM
21
Leakage now dominated by imperfect isolation
IOFF,min (pA/m)
100
Wg = 7 um
Wg = 10 um
75
Wg = 25 um
VDS = 0.5 V
3.5x
50
25
2.5x
0
0
100 200 300 400 500 600
Gate length (nm)
Leakage current is independent of gate width
→ leakage now dominated by imperfect device isolation, by edges of device mesa.
22
Refractory Contacts to In(Ga)As
Baraskar et al, Journal of Applied Physics, 2013
-5
B=0.3 eV
P-InGaAs
N-InGaAs
0.2 eV
0.1 eV
N-InAs
-6
Contact Resistivity, cm
2
10
10
-7
10
-8
10
-9
10
-10
10
B=0.8 eV
B=0.6 eV
18
19
B=0 eV
0.6 eV
0.4 eV
0.2 eV
step-barrier
Landauer
0.4 eV
0.2 eV
0 eV
step-barrier
Landauer
20
21
10
10
10
10
-3
Electron Concentration, cm
18
19
step-barrier
Landauer
20
21
10
10
10
10
-3
Hole Concentration, cm
18
19
20
21
10
10
10
10
-3
Electron Concentration, cm
Refractory: robust under high-current operation / Low penetration depth: ~ 1 nm / Performance sufficient for 32 nm /2.8 THz node.
State-of-art in III-V contacts: ~5*10-9 -cm2
Key: high doping, clean surfaces, high indium content for N-type
23
III-V on Si
Ultrathin InAs-Channel MOSFETs
on Si Substrates
Cheng-Ying Huang1, Xinyu Bao2, Zhiyuan Ye2, Sanghoon Lee1,
Hanwei Chiang1, Haoran Li1, Varistha Chobpattana3, Brian
Thibeault1, William Mitchell1, Susanne Stemmer3, Arthur
Gossard1,3, Errol Sanchez2, and Mark Rodwell1
1ECE,
University of California, Santa Barbara
2Applied Materials, Santa Clara
3Materials Department, University of California, Santa Barbara
VLSI-TSA 2015
HsinChu, Taiwan
Applied Materials III-V buffer on Si
Rq=3.1 nm
RHEED in MBE
26
UCSB III-V FET epitaxy
Surface roughness is degraded
after FET epitaxy.
Rq= 6.9 nm
27
TEM images of III-V FET on Si
LLg~20nm
g~20nm
28
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
2.4
VDS = 0.1 to 0.7 V, step 0.2 V
SS ~ 142.4 mV
SS ~ 100.8 mV
1.5
1.6
1.2
0.8
VGS = -0.2 V to 1.0 V
0.2 V increment
Ron = 294 Ohm-m
2.0
ID (mA/m)
10
gm (mS/m)
ID (mA/m)
Short gate length: Lg-20 nm
1.0 at V = 1.0 V
GS
0.5
0.4
-0.2
0.0
0.2
0.4
0.6
0.0
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VGS (V)
VDS (V)
• High Gm~2.0 mS/μm at VD=0.5 V.
• SS~140 mV/dec. at VD=0.5 V and 101 mV/dec. at VD=0.1 V
• High Ion >1.4 mA/um at VGS=1V.
29
Future Work
Future Work: High Current & Low Leakage
Wide-gap spacer near channel: reduces BTBT
Upper spacer: improves electrostatics
Thick InP spacers add source resistance, reduce Ion.
Solution: composite InP/InGaAs spacer with InGaAsP grades
31
Future Work: High Current & Low Leakage
finFETs: better electostatics→ thick spacers not needed
Need only thin InP spacer to supress BTBT
→ improved on-current
InP spacer formed during S/D regrowth.
32
finFET with surface vs. bulk inversion.
16 meV energy
splitting
3nm InAs well
1.5nm AlAs
barrier
3nm InAs well
Cohen-Elias et al., DRC 2013
33
Next: Superlattice Steep FETs
Objective: low-power VLSI
0.1-0.2 V operation
>10:1 less switching energy
Approach: superlattice FET
energy filter in source
MOVCD regrowth
Impact: low-voltage,
high on-current (>> than T-FET)
→ fast, ultra-low-power VLSI logic
We can make it work.
Long et al., (Purdue/UCSB) IEEE EDL, December 2014
34
How we might build a superlattice FET
A simple extension of present planar III-V MOS process flow...
III-V MOS
For high-performance applications (Ioff=100nA/m)
on-currents substantially better than Si at VDD=0.5V
Lower-power applications (SP/LP/UPL)
target off-currents as small as 10pA/m
InP spacers can provide such small leakage
Problem: incrased access resistance, reduced Ion
Best solution:
Thin (2-5nm) InP spacers in finFETs
fin geometry fixes electrostatics
InP spacers fix BTBT.
36
(end)