Record Ion (0.50 mA/μm at VDD = 0.5 V and Ioff = 100 nA/μm)
25 nm-Gate-Length ZrO2/InAs/InAlAs MOSFETs
Sanghoon Lee1*, V. Chobpattana2,C.-Y. Huang1, B. J. Thibeault1, W. Mitchell1,
S. Stemmer2, A. C. Gossard2, and M. J. W. Rodwell1
1ECE
and 2Materials Departments
University of California, Santa Barbara, CA
2014 Symposium on VLSI Technology
Honolulu, Hawaii, USA
06/10/2014
*sanghoon_lee@ece.ucsb.edu
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VLSI 2014
Why III-V MOSFETs in VLSI applications?
Low m* in III-V material  high vinj
 high transconductance
More transconductance per gate width
more current  lower intrinsic delay
-or- reduced VDD  less power consumption
-or- small FETs  reduced IC size
TW. Kim, IEDM 2012
Other advantages
Wide range of available materials
nm-precise growth  1-2 nm thick channel
Larger ΔEc Better confinement, Small EOT
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VLSI 2014
Key Design Considerations
Dielectric:
Source/Drain:
Low ρc  Small contact size
Self-aligned  Small contact pitch
Shallow  Scaling (electrostatics)
N+Source
Dielectric
Channel
Thin high Ion, better SS and DIBL
Low Dit  Better SS
N+Drain
Barrier
Channel:
Thin  Electrostatics
Thin and wide bandgap  Small band-band tunneling
Thick and narrow bandgap  higher injection velocity
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VLSI 2014
FET Structures
N+Source
Dielectric
N+Drain
N+Source
Body
- Self-aligned
- Implant damage
- Large Raccess (limited doping)
N+Source
Channel
- Good short channel effect
- Large device footprint
- Large Raccess (Barrier)
Dielectric
Channel
Etch stop
Barrier
MOS-HEMT
N+Source
(Regrown)
N+Drain
Dielectric
Barrier
Inversion layer
Inversion mode MOSFETs
N+Drain
Dielectric
Barrier
Channel
Trench-etch
- Small footprint
- Small Raccess
- Limited Lg scaling (wet etch)
N+Drain
(Regrown)
Barrier
Regrown S/D with gate-Last
Regrown S/D with gate-first
- Small footprint and Lg
- Small Raccess
- Abrupt junction
- Low damage (No dry etch)
- High damage (gate-stack etch)
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VLSI 2014
Gate-Last Process ( Simplified for Development )
Channel growth
By MBE
Dummy gate formation
e-beam lithography
Cap: 2 nm In0.53Ga0.48As (U.I.D)
Channel : 3.5 nm InAs (Strained)
Setback: In0.52Al0.48As Setback (U.I.D)
Pulse Doping (Si 2X1012 /cm2)
Back Barrier: In0.52Al0.48As (U.I.D)
P-type Doped Barrier: In0.52Al0.48As
(Be 1017/cm3)
50 nm N+
In0.53Ga0.47As
HSQ
Regrown S/D
HSQ
10 nm In0.53Ga0.47As
Al2O3
InGaAs Cap
InAs Channel
In0.52Al0.48As Setback
Vertical Spacer
Al2O3
InGaAs Cap
InAs Channel
In0.52Al0.48As Setback
In Al As Back Barrier Pulse Doping
In0.52Al0.48As Back Barrier Pulse Doping
0.52
0.48
P-type Doped Barrier
P-type Doped Barrier
Substrate: InP (Semi-insulating)
Mesa-isolation
Surface digital etching
Vertical spacer and N+ S/D
regrowth in MOCVD
InP (Substrate)
InP (Substrate)
Gate stack formation
S/D metal contact formation
0.7/3.0 nm Al2OxNy/ZrO2
0.7/3.0 nm Al2OxNy/ZrO2
Ti/Pd/
Au
N+ In0.53Ga0.47As
Regrown S/D
12 nm In0.53Ga0.47As
Vertical Spacer
2.5 nm InAs Channel
In0.52Al0.48As Setback
In0.52Al0.48As Back Barrier Pulse Doping
P-type Doped Barrier
InP (Substrate)
Ni/Au
(gate metal)
N+ In0.53Ga0.47As
12 nm In0.53Ga0.47As
Regrown S/D
Vertical Spacer
2.5 nm InAs Channel
In0.52Al0.48As Setback
In0.52Al0.48As Back Barrier Pulse Doping
P-type Doped Barrier
InP (Substrate)
5
(S/D
metal)
LSD
Ni/Au
(gate metal)
N+ In0.53Ga0.47As
12 nm In0.53Ga0.47As
Lg
Regrown S/D
Vertical Spacer
2.5 nm InAs Channel
In0.52Al0.48As Setback
In0.52Al0.48As Back Barrier Pulse Doping
P-type Doped Barrier
InP (Substrate)
VLSI 2014
High-k : MOSCAP with 0.7/5.0 nm Al2OxNy/ZrO2
Ni/Au
54 nm ZrO
ZrO22
~0.7 nm Al2OxNy
N-type In0.53Ga0.47As
N-type InP (Substrate)
Cr/Au
MOSCAP structure
 dielectric constant for ZrO2 is 23; EOT is ~1 nm
 3.5 µF/cm2 accumulation capacitance at 1MHz
 ~1X1012 /cm2-eV Dit near midgap.
 Gate leakage < 1 A/cm2 up VG=2 V
(V. Chobpattana, et al., ‘Scaled ZrO2 dielectrics for InGaAs gate stack with low interface trap densities’, APL 2014)
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VLSI 2014
Off-state leakage and S/D spacers
MOS-HEMT with large contact pitch
Small S/D contact pitch
0
10
-1
10
3.2
Lg = 18 nm
2.8
VDS = 0.1, 0.5 V
2.4
2.0
-2
10
1.6
-3
1.2
10
0.8
-4
10
0.4
-5
10
-0.2
Lg =35 nm
gm (mS/m)
Current Density (mA/m)
Band-band tunneling
impact ionization
0.0
0.2
0.4
0.0
Gate Bias (V)
D-H. Kim, IEDM 2012
Large lateral spacer  low leakage, good short channel immunity
Large lateral spacer  large S/D pitch
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VLSI 2014
Vertical Spacers  reduced off-state leakage
200
Spacer thickness
2 nm
7 nm
12 nm
SSmin (mV/dec)
180
160
Open: VDS = 0.1 V
140
Solid: VDS = 0.5 V
120
100
80
60
0.01
Spacer
SSmin (mV/dec)
180
160
Open: VDS = 0.1 V
140
Solid: VDS = 0.5 V
120
100
/m)
 Larger spacer
80
60 and long channels
 better short channel effect at short
0.01
0.1
1
10
10
0
-1
Gate Length (m)
2 nm
8
10
-1
10
-2
10
-3
10
-4
10
-5
2 nm
7 nm
Spacer thickness
2 nm
7 nm
12 nm
250
DIBL (mV/V)
Spacer thickness
2 nm
7 nm
12 nm
10
7 nm
1
Gate Length (m)
0
300
Current Density (mA/m)
200
0.1
200
150
100
50
-6
V
= 0.1 to 0.7 V
10 at 1 DS
A/m
0
-7
0.01
10
0.2 V increment
0.1
1
length0.4
(m) 0.0
0.0Gate0.2
Gate
(S. Lee, et al., EDL, June 2014)
12 nm
VLSI 2014
Cross-sectional STEM image
Courtesy of S. Kraemer (UCSB)
9
*Heavy elements look brighter
VLSI 2014
-2
10
Dot : Reverse Sweep
Solid: Forward Sweep
Lg = 1 m
10
1
10
0
10
-1
10
-2
10
-3
-3
10
-4
10
-5
10
-6
10
-7
10
-8
SSmin~ 61 mV/dec.
(at V
DS
= 0.1 V)
SSmin ~ 63 mV/dec. 10-4
(at V
= 0.5 V)
10
10
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DS
-5
2
Current Density (mA/m)
-1
10
|Gate Leakage| (A/cm )
I-V characteristics for long channel device (Lg = 1 µm)
Gate Bias (V)
 61 mV/dec Subthreshold swing at VDS=0.1 V
 Negligible hysteresis
 <1 A/cm2 gate leakage at measured bias range
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VLSI 2014
Current Density (mA/m)
2.8
Lg = 25 nm
2.4
0.8 Ion= 500 A/m
(at
0.6
I =100 nA/m, V =0.5 V)
off
DD
VDS = 0.1 to 0.7 V
0.2 V increment
2.0
1.6
1.2
0.4
0.8
0.2
0.4
0.0
0.0
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
10
1
10
0
-1
10
VDS = 0.1 to 0.7 V
0.2 V increment
-3
10
-4
DIBL = 76 mV/V
-5
VT = -85 mV at 1 A/m
-6
SSmin~ 72 mV/dec. (at VDS = 0.1 V)
-7
SSmin~ 77 mV/dec. (at VDS = 0.5 V)
10
1.0
VGS = -0.4 V to 0.7 V
0.1 V increment
Ron = 303 Ohm-m
0.8 at V = 0.7 V
GS
LSD = 140 nm
Lg = 25 nm
0.6
0.4
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Drain Bias (V)
Lg = 25 nm
-2
10
1.2
Gate Bias (V)
10
10
Current Density (mA/m)
1.0
gm (mS/m)
Current Density (mA/m)
I-V characteristics for short channel devices ( Lg = 25 nm)
 ~2.4 mS/μm Peak gm at VDS=0.5 V
 ~300 Ohm-µm on-resistance at VGS=0.7 V
 77 mV/dec Subthreshold Swing at VDS=0.5 V,
76 mV/V DIBL at 1 µA/µm
 0.5 mA/µm Ion at Ioff=100 nA/µm and VDD=0.5 V
10
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
Gate Bias (V)
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VLSI 2014
N+S/D
RRaccess
Rspacer
Rballistic
5000
800
Ron = 168 -m (+/- 25 -m)
4000
Resistance (Ohm-m)
Rcontact
On-Resistance (Ohm-m)
Source/drain series resistance
(extrpolated at zero Lg)
3000
2000
1000
at VGS = 0.7 V
0
0.0
0.2
0.4
0.6
0.8
600
Gate Length (m)
RN+SD= 85 -m
500
400
300
Gap
Ti/Pd/Au
200
60 nm N+ InGaAs
(regrown contact layer)
100
0
1.0
Y = 24 + 25*X
2
c = 5.3 -m
700
5 nm Intrinsic InGaAs (Capping layer)
Channel
0
5
10
15
Gap (m)
20
25
Rcontact
[Ohm-µm]
RN+ S/D
[Ohm-µm]
Rspacer
[Ohm-µm]
Rballistic
[Ohm-µm]
Ron at zero
Lg[Ohm-µm]
25
60
35
50
170
for both source and drain sides
 From TLM measurement for N+S/D, RN+S/D sheet = 25 ohm/sq, ρc= ~5.3 ohm-μm2
 Rspacer is estimated to be ~35 ohm-μm for both sides
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VLSI 2014
Performance comparison: 2.5 nm VS 5.0 nm-thick channel
2.5 nm InAs
5.0 nm InAs
2.5 nm InAs
100
Open: VDS = 0.1 V
90
Solid: VDS = 0.5 V
80
70
0.1
Gate Length (m)
1
Current Density (mA/m)
SSmin (mV/dec)
110
60
0.01
5.0 nm InAs
0
10
SS ~ 60 mV/dec
-1
10 at V =0.1 V
-2
DS
10 Lg =500 nm
-3
10
ID
-4
10
SS ~ 64 mV/dec
at VDS=0.1 V
Lg =500 nm
ID
-5
10
-6
10
-7
10
-8
10
IG
IG
-9
10
-10
10
-0.2 0.0
0.2
0.4 -0.2 0.0
Gate Bias (V)
0.2
0.4
Gate Bias (V)
 Better SS at all gate length scale:
 Better electrostatics, reduced BTBT
 ~1:10 reduction in minimum off-state leakage
 ~5:1 increase in gate leakage  increased eigenstate
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VLSI 2014
Performance comparison: 2.5 nm VS 5.0 nm-thick channel
2.8
1200
InAs channel thickness
2.5 nm
5.0 nm
1.2
0.8
400
200
VDS = 0.5 V
0
7
2.0
W/L= 25m/21 m
2
Cox = 4.2 F/cm
6
5
EOT= 0.8 nm
1.5
4
1.0
3
2
0.5
2.5 nm InAs
5.0 nm InAs
0.0
0.2
0.4
Gate Bias (V)
0.6
1
Energy (eV)
Freq: 200kHz
Carrier Density (/cm )
Gate Length (m)
0
1
12
0.1
2.5
0.0
-0.2
600
x 10
0.4
800
2
1.6
0.0
0.01
Gate Capacitance (F/cm2)
eff (cm /s-V)
2.0
1000
2
Peak gm (mS/m)
2.4
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
2.5 nm InAs
5.0 nm InAs
1
2
3
4
5
6
Carrier Density (/cm2)
~1.25 nm
EF
E1
2.5 nm thick
10
20
30
Position (nm)
0
7
12
x 10
~2.5 nm
EF
E1
5 nm thick
10
20
30
Position (nm)
1D-Possion Schrodinger solver
(coded by W. Frensley, UT Dallas)
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VLSI 2014
SS and DIBL vs. Lg (Benchmarking)
[2]
[4]
[3]
[7]
[1]
[6]
[5]
SSmin (mV/dec.)
Open: VDS = 0.1 V
110
100
90
80
Planar
[6]
[3]
[1]
Tri-gate or GAA
[2]
[4]
[7]
140
120
DIBL (mV/V)
Solid: VDS = 0.5 V
120
100
80
60
40
This work
20
70
This work
60
0.01
0
0.1
1
0
40
80
120
160
Gate Length (nm)
Gate Length (m)
[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013
[5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009
 <80 mV/dec at sub-30 nm Lg and VDS=0.5 V
 Record low subtheshold swing among any reported III-V FETs.
 Lowest DIBL among planar-type III-V FETs.
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VLSI 2014
Peak gm and Ion at fixed Ioff vs. Lg (Benchmarking)
0.50
VDS = 0.5 V
0.45
2.4
2.0
Ion (mA/m)
Peak gm (mS/m)
2.8
1.6
[5]
[6]
[7]
[3]
[4]
[1]
1.2
0.8
0.4
0.0
0.01
VDD = 0.5 V
This work
0.40
0.35
0.30
This work
J. Lin, IEDM2013
T. Kim, IEDM2013
Intel, IEDM2011
Intel, IEDM2009
J. Gu, IEDM2012
D. Kim, IEDM2012
0.25
0.20
0.15
This work
0.1
Gate Length (m)
Ioff = 100 nA/m
0.10
1
100
Gate Length (nm)
[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013
[5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009
 >2.4 mS/µm peak gm at VDS=0.5 V and sub-30 nm Lg.
 Highest Ion at Ioff=100 nA/µm and VDD=0.5 V
 0.5 mA/µm Ion at sub-30 nm Lg
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VLSI 2014
Benchmark with 22 nm node Si Fin- and nanowire FET
Intel 22 nm Si FinFET
IBM 22 nm nanowire FET
S. Bangsaruntip et al., IEDM 2013
Jan, IEDM 2012
 Intel 22 nm FinFETs (HP) : ~0.5 mA/µm (?) @ VGS=0.5 V, VDS=0.75 V
 IBM 22 nm nanowire : ~0.4 mA/µm @ VGS=0.5 V, VDS=0.5 V
 Comparable performance with state-of-the-art Si-FinFETs (nanowire).
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VLSI 2014
Conclusion
 Developed vertical spacer to reduce off-state leakage and to
improve short channel effect.
 Integrated sub-1 nm EOT ZrO2 high-k with low Dit
 Obtained 61 mV/dec at VDS =0.1 V and 1 μm-Lg.
 Obtained 0.5 mA/μm at Ioff =100 nA/μm and VDD =0.5 V
(best reported Ion among any reported III-V MOSFETs)
 Achieved comparable Ion to state-of-art multi-gate Si-FETs
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VLSI 2014
Acknowledgment
Thanks for your attention!
Questions?
This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006).
A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and
MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.
*sanghoon_lee@ece.ucsb.edu
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VLSI 2014