IPRM/ISCS Conference, June 30-July , 2015, UCSB
III-V MOS:
Record-Performance Thermally-Limited Devices,
Prospects for
High-On-Current Steep Subthreshold Swing Devices
Mark Rodwell, UCSB
III-V MOS
C.-Y. Huang, S. Lee*, A.C. Gossard,
V. Chobpattanna, S. Stemmer, B. Thibeault, W. Mitchell : UCSB
Low-voltage devices
P. Long, E. Wilson, S. Mehrotra, M. Povolotskyi, G. Klimeck: Purdue
Now with: *IBM, **Intel
1
Why III-V MOS ?
III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering
→ higher current. Can then trade for lower voltage or smaller FETs.
Problems: Low m*→ less charge. Low m* → more S/D tunneling.
Narrow bandgap→ more band-band tunneling, impact ionization.
2
Reducing leakage: Vertical spacer, Ultra-thin channel
N+ S/D
Vertical Spacer
Courtesy of S. Kraemer (UCSB)
*Heavy elements look brighter
Lee et al., 2014 VSLI Symposium 3
S. Lee et al., VLSI 2014
1.2
1.0
VGS = -0.4 V to 0.7 V
Current Density (mA/m)
Current Density (mA/m)
Reducing leakage: Vertical spacer, Ultra-thin channel
0.1 V increment
Ron = 303 Ohm-m
0.8 at V = 0.7 V
GS
0.6
0.4
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Drain Bias (V)
SSmin (mV/dec.)
110
100
90
80
Ion (mA/m)
[2]
[4]
[3]
[7]
[1]
[6]
[5]
Open: VDS = 0.1 V
Gate Length (m)
0
10
Lg = 25 nm
VDS = 0.1 to 0.7 V
0.2 V increment
-2
10
-3
10
-4
DIBL = 76 mV/V
-5
VT = -85 mV at 1 A/m
-6
SSmin~ 72 mV/dec. (at VDS = 0.1 V)
-7
SSmin~ 77 mV/dec. (at VDS = 0.5 V)
10
10
10
10
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
0.50
VDS = 0.5 V
0.45
Ioff=100 nA/m
0.40
0.35
0.30
0.25
0.20
0.10
This work
0.1
10
-1
0.15
70
60
0.01
1
Gate Bias (V)
Solid: VDS = 0.5 V
120
10
1
10
S. Lee, VLSI 2014
J. Lin, IEDM 2013
T. Kim, IEDM 2013
Intel, IEDM 2009
J. Gu, IEDM 2012
D. Kim, IEDM 2012
100
Gate Length (nm)
[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013
[5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009
4
Off-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel
2.5 nm InAs
5.0 nm InAs
2.5 nm InAs
100
Open: VDS = 0.1 V
90
Solid: VDS = 0.5 V
80
70
0.1
Gate Length (m)
1
Current Density (mA/m)
SSmin (mV/dec)
110
60
0.01
5.0 nm InAs
0
10
SS ~ 60 mV/dec
-1
10 at V =0.1 V
DS
-2
L
=500
nm
10
g
SS ~ 64 mV/dec
at VDS=0.1 V
Lg =500 nm
-3
10
-4
10
ID
ID
-5
10
-6
10
-7
10
-8
10
IG
IG
-9
10
-10
10
-0.2 0.0
0.2
0.4 -0.2 0.0
Gate Bias (V)
0.2
0.4
Gate Bias (V)
Better SS at all gate lengths
 Better electrostatics (aspect ratio) and reduced BTBT (quantized Eg)
~10:1 reduction in minimum off-state leakage
~5:1 increase in gate leakage  increased eigenstate
5
On-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel
2.8
1200
InAs channel thickness
2.5 nm
5.0 nm
1.2
0.8
400
200
VDS = 0.5 V
0
7
2.0
W/L= 25m/21 m
2
Cox = 4.2 F/cm
6
5
EOT= 0.8 nm
1.5
4
1.0
3
2
0.5
2.5 nm InAs
5.0 nm InAs
0.0
0.2
0.4
Gate Bias (V)
0.6
1
0
Energy (eV)
Freq: 200kHz
Carrier Density (/cm )
Gate Length (m)
0
1
12
0.1
2.5
0.0
-0.2
600
x 10
0.4
800
2
1.6
0.0
0.01
Gate Capacitance (F/cm2)
eff (cm /s-V)
2.0
1000
2
Peak gm (mS/m)
2.4
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
2.5 nm InAs
5.0 nm InAs
1
2
3
4
5
6
Carrier Density (/cm2)
~1.25 nm
EF
E1
2.5 nm thick
10
20
30
Position (nm)
7
12
x 10
~2.5 nm
EF
E1
5 nm thick
10
20
30
Position (nm)
1D-Possion Schrodinger solver
(coded by W. Frensley, UT Dallas)
6
ZrO2 vs. HfO2: Peak gm, SS, split-CV, and mobility
Comparison: two process runs ZrO2 , one run HfO2 , both 2nm (on 1nm Al2O3)
VDS = 0.5 V
1.6
0.8
0425A1 (30A ZrO2)
0425A2 (30A HfO2)
VLSI (30A ZrO2)
0.4
0.1
2.0
1.5
7
W/L= 25m/21 m
6
ZrO2
HfO2
5
4
3
1.0
2
0.5
0.0
1
0.0
0.2
0.4
Gate Bias (V)
0.6
0
2
Freq: 200kHz
Carrier Density (/cm )
x 10
Gate Length (m)
1
SSmin (mV/dec)
1.2
2.5
VLSI (30A ZrO2)
0425A1 (30A ZrO2)
0425A2 (30A HfO2)
85
0.0
0.01
Gate Capacitance (F/cm2)
90
2.0
12
Peak gm (mS/m)
2.4
80
75
70
65
Open: VDS = 0.1 V
60 Solid: V = 0.5 V
DS
0.01
0.1
Gate Length (m)
1
(1) ZrO2 higher capacitance than HfO2 , (2) ZrO2 results, low SS, are reproducible
7
Double-heterojunction MOS: 60 pA/m leakage
Lg-30nm
Lg-30nm
C. Y. Huang et al., IEDM 2014
•
•
•
Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm
100:1 smaller Ioff compared to InGaAs spacer
BTBT leakage suppressedisolation leakage dominates
8
12 nm Lg III-V MOS
Lg~12nm
N+InGaAs
~ 8nm
Cross-setion
N+InP
Ni
InP spacer
Top View
InAlAs
Barrier
tch~ 2.5 nm
(1.5/1 nm InGaAs/InAs)
9
ID-VG and ID-VD curves of 12nm Lg FETs
Lg-12nm
1.0
2.4
VDS = 0.1 to 0.7 V,
2.0
0.2 V increment
1.6
0.6
1.2
0.4
0.8
0.2
0.0
10
Ioff~1.3 nA/μm
V = 0.1 to 0.7 V
1
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
1.5
0.2 V increment
SS ~ 107.5 mV
at VDS=0.5 V
SS ~ 98.6 mV
at VDS=0.1 V
-0.2
0.0
0.4
0.0
0.2
0.4
VGS (V)
VGS = -0.2 V to 1.2 V
DS
0.2
0.4
V
(V)
0.6
0.8
ID (mA/m)
ID, |IG| (mA/m)
10
0
1.0
gm (mS/m)
ID (mA/m)
0.8
0.6
0.8
0.0
Ion~1.1 mA/μm
0.2 V increment
Ron = 302 Ohm-m
at VGS = 1.0 V
Ion/Ioff > 8.3∙105
0.5
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VDS (V)
10
8
2
1.5/1 nm InGaAs/InAs
2.0
6
1.5
4
1.0
2
0.5
0.4
0.6
0
1.0
0.8
)
0.2
-2
0.0
0.0
12
Cacc (F/cm )
EOT~ 0.9~1 nm
VGS (V)
500
Mobility~ 250 cm2/V∙s
12
2.0
W/L= 25m/21 m
2
Cox = 4.2 F/cm
6
5
EOT= 0.8 nm
1.5
4
1.0
3
2
0.5
1
2.5 nm InAs
5.0 nm InAs
0.0
-0.2
0.0
0.2
0.4
Gate Bias (V)
0
0.6
800
2
eff (cm /s-V)
2
Mobility (cm /Vs)
7
1000
300
200
100
0
Freq: 200kHz
1200
VDS = 25 mV to 50 mV
400
2.5
Carrier Density (/cm )
Freq: 200 kHz
2.5 0.2 V increment
Carrier density (10 cm
VDS = 0.1 to 0.7 V
InAs channel
x 10
10
2
This work
3.0
Gate Capacitance (F/cm2)
Mobility extraction at Lg-25 µm long channel FETs
1.5/1 nm InGaAs/InAs
0
1
2
3
4
5
6
-2
Carrier density (cm )
600
400
Mobility~ 280 cm2/V∙s
200
0
0
m*, RS/D more important!
2.5 nm InAs
5.0 nm InAs
1
2
3
4
5
6
Carrier Density (/cm2)
7
12
x 10
11
Steep FETs
12
Tunnel FETs: truncating the thermal distribution
Normal
T-FET
J. Appenzeller et al.,
IEEE TED, Dec. 2005
Source bandgap truncates thermal distribution
Must cross bandgap: tunneling
Fix (?): broken-gap heterojunction
13
Tunnel FETs: are prospects good ?
Useful devices must be small
Quantization shifts band edges→ tunnel barrier
Band nonparabolicity increases carrier masses
Electrostatics: bands bend in source & channel
What actual on-current might we expect ?
14
Tunneling Probability
Transmissi on Probabilit y (WKB, square barrier)
P  exp( 2Tbarrier ), where  
2m * Ebarrier

Assume : m*  0.06  m0 , Eb  0.2 eV
Then :
P  33% for a 1nm thick barrier
 10% for a 2nm thick barrier
 1% for a 4nm thick barrier
For high Ion, tunnel barrier must be *very* thin.
~3-4nm minimum barrier thickness:
P+ doping, body & dielectric thicknesses
15
T-FET on-currents are low, T-FET logic is slow
NEMO simulation:
1.5
0.4
1
0.3
0.5
0
-0.5
-1
2
10
0.2
0.1
0
3.0%
-0.1
-1.5
5
10
15
20
25
position, nm
Experimental:
InGaAs heterojunction HFET;
drain current, A/m
2
0.5
Energy(eV)
Energy, eV
GaSb/InAs tunnel finFET: 2nm thick body, 1nm thick dielectric @ er=12, 12nm Lg
-0.2
-3
10
-2
-1
10
10
10
Transmission
0
60mV/dec.
1
10
0
10
10
-1
10
-2
10
-3
10
-4
10
-5
10 A/m
0
0.1 0.2 0.3 0.4 0.5 0.6
gate-source bias, volts
~15 A/m @0.7V
Dewey et al,
2011 IEDM,
2012 VLSI Symp.
Low current
→ slow logic
16
Resonant-enhanced tunnel FET
Avci & Young, (Intel) 2013 IEDM
2nd barrier: bound state
dI/dV peaks as state aligns with source
improved subthreshold swing.
Can we also increase the on-current ?
17
Electron anti-reflection coatings
Tunnel barrier:
transmission coefficient < 100%
reflection coefficient > 0%
want: 100% transmission, zero reflection
familiar problem
Optical coatings
reflection from lens surface
quarter-wave coating, appropriate n
reflections cancel
Microwave impedance-matching
reflection from load
quarter-wave impedance-match
no reflection
Smith chart.
18
T-FET: single-reflector AR coating
drain current, A/m
0.5
Energy(eV)
0.4
0.3
0.2
0.1
0
-0.1
TFET
TFET+ one barrier
-0.2
-3
10
10
2
10
1
10
0
60mV/dec.
-1
10
-2
10
-3
10
-4
10
-5
TFET
+one barrier
10
-2
-1
10
10
10
Transmission
0
0 0.1 0.2 0.3 0.4 0.5
gate-source bias, volts
Peak transmission approaches 100%
Narrow transmission peak; limits on-current
Can we do better ?
19
Limits to impedance-matching bandwidth
Microwave matching:
More sections→ more bandwidth
Is there a limit ?
Transmission, dB
1
1, 2, 3 sections
0
-1
-2
-3
-4
-5
-6
-7
Bode-Fano limits
0
5
10
15
20
Frequency, GHz
R. M. Fano, J. Franklin Inst., Jan. 1960
Bound bandwidth for high transmission   1 



ln
d


example: bound for RC parallel load→  
2 
||

||
RC


Do electron waves have similar limits ? 0
Yes ! Schrödinger's equation is isomorphic to E&M plane wave.
Khondker, Khan, Anwar, JAP, May 1988
T-FET design→ microwave impedance-matching problem
Fano: limits energy range of high transmission
Design T-FETs using Smith chart, optimize using filter theory
Working on this: for now design by random search
*E / h  f ,   V ,   I , probabilit y current  power, where  ( x)  ( / jm*)( / x) 20
T-FET with 3-layer antireflection coating
10
0.25
2
Simulation
2
1
10
0.5
0
drain current, A/m
1
Energy(eV)
Energy, eV
1.5
3-layer
0-layer
0.2
0.15
-0.5
-1
0
10
-1
10
-2
60mV/dec.
triple layer
-3
single layer
-4
P-GaSb/N-InAs
tunnel FET
10
10
10
-1.5
5
10
15 20 25
position, nm
30
35
0.1
-5
10
-3
10
-2
10
-1
10
Transmission
Interim result; still working on design
0
10
0
0.1 0.2 0.3 0.4 0.5
gate-source bias, volts
0.6
21
Source superlattice: truncates thermal distribution
Proposed 1D/nanowire device:
M. Bjoerk et al., U.S. Patent 8,129,763, 2012.
Gnani, 2010 ESSDERC
E. Gnani et al., 2010 ESSDERC
Gnani, 2010 ESSDERC:
simulation
22
Long et al., EDL, Dec. 2014
Planar (vs. nanowire) superlattice steep FET
Planar superlattice FET
superlattice by ALE regrowth
easier to build than nanowire (?)
Performance (simulations):
~100% transmission in miniband.
0.4 mA/m Ion , 0.1A/m Ioff ,0.2V
Ease of fabrication ?
Tolerances in SL growth ?
Effect of scattering ?
simulation
23
(backup slides follow)
24