EENG211/INFE211
Digital Logic Design
Experiment 5
Decoders/Demultiplexers and Multiplexers
#
1
2
Student No
Name Surname
Sign
Objective:
1. Testing the operation of 74x138 decoder. And using it as demultiplexer.
2. Implementing Boolean functions using 74x138 decode.
3. Testing the operation and implementing Boolean functions using 74151 multiplexer.
USED ICs: 74LS138, 74151, 7410, 7404
DATA INPUTS
VCC
16
4
DATA SELECT
5
6
7
A
B
C
15
14
13
12
11
10
9
D4
D5
D6
D7
A
B
D3
74151
C
D2
D1
D0
Y
W
S
1
2
3
4
5
6
7
3
2
1
0
Y
W STROBE
DATA INPUTS
8
GND
OUTPUTS
74138 3-line to 8-line decoder/demultiplexer
74151 8-line to 1-line data multiplexer
7410 3-input NAND
7404 Hex Inverter
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EENG211/INFE211
Digital Logic Design
Decoder Implementation
1)
The following figure shows the pin numbers of 74138 decoder. The enable inputs
, and
are connected to
–
. The select inputs A, B, & C are connected to
–
. The outputs
–
are connected to L0 – L7.
NOTE: The output is active low.
Table 1
G2A
G2B
G1
Select
Input
C B A
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X X X
X X X
X X X
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Enable Input
Output
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
74138 Decoder Pin-out Diagram
2)
Function Implementation with a decoder:
A combinational circuit has three inputs A, B and C, and three outputs F1, F2, and F3.
The simplified Boolean functions for the circuit are as follows:
In order to implement the three functions, we need a 3x8 decoder, with A, B and C beig
connected to the input lines of the decoder. The first step is to write each of the functions
a sum of minterms. In fact, the decoder will generate all the minterms, so to implement a
function, we choose the minterms that represent this function, and send them to an OR
gate.
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EENG211/INFE211
Digital Logic Design
Since the 74138 decoder generates complemented outputs, we need to complement them
before they reach the input side of the OR gate. This is equivalent to feeding theses
complemented outputs to a NAND gate.
2.1)
Connect and check the following circuit which implementsF1 and F2, using 74138 decoder and
NAND gate. Record your data in table 2.
NOTE: The output is active low; inverters are connected to the output before using or gate.
Invert OR = NAND.
Table 2
Enable
Input
Select Input
Output
G2A
G2B
G1
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-3-
F1
F2
EENG211/INFE211
Digital Logic Design
2.2) Implement and show the simplified 2.3) Construct a 4 x 16 line decoder
Boolean functions:
using two 3 x 8 line decoders
with enable.
Multiplexers:
1) The following figure shows the block diagram of the 74151 MUX. Verify truth table 3 of
the MUX. Apply the inputs
with data switches SW0 – SW2.
Table 3
Strobe
S
1
0
0
0
0
0
0
0
0
C
X
0
0
0
0
1
1
1
1
Select
B
X
0
0
1
1
0
0
1
1
A
X
0
1
0
1
0
1
0
1
Output
Y
0
D0
D1
D2
D3
D4
D5
D6
D7
Q2) Explain how the multiplexer can be used as a parallel to serial converter?
………………………………………………………………………………………………
………………………………………………………………………………………………
………………………………………………………………………………………………
-4-
EENG211/INFE211
Digital Logic Design
2) Implement the following Boolean function with an 8x1 multiplexer:
. Apply the inputs
with data switches
SW0 – SW3 and the output at L0 as indicated in table 4.
The connection is done as follows:
The variables
and are connected to the selection lines of the MUX.
The inputs of the MUX are functions of the fourth variable z, as follows:
MUX
inputs
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
y
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
8
D0=1
1
9
D1=z
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
w Output
0
1
1
D
0
0
1
D'
0
0
1
D'
0
1
1
D
0
1
1
D
0
0
1
D'
0
0
1
D'
0
1
1
D
2
10
D2=0
3
11
D3=z’
4
12
D4=0
5
13
D5=z’
6
14
D6=1
Fall 2012-2013, EENG 115(EENG 211)/INFE 115(INFE 211) Digital Logic Design I, Lab Report.
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7
15
D7=z