Progress Report
C.C. Li 2007/05/10
What I have done this week
1. Survey paper：
[1] A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC
Codes
A memory efficient partially parallel decoder architecture suited for high rate
Quasi-Cyclic Low- Density Parity-Check codes using (modified) Min-Sum
decoding algorithm is proposed.The optimized partially parallel decoder architecture
can linearly increase the decoding throughput with small hardware overhead.
Consequently, the proposed approach facilitates the applications of LDPC codes in
area/power sensitive high speed communication systems.
In check-to-variable message updating phase, for each row c , three kind of
messages
,
and I v , where
, are sent to the v-th VPU via the path
indicated by the dashed line to compute
. Then, all of the intermediate results
calculated by the K VPUs are sent to CPU. Finally, the compressed check-to-variable
messages for the K block columns are generated and stored into one entry of the
R-memory. In the variable-to-check message updating phase, the summation of
check-to-variables for each column of H matrix is accumulated. For each row c, the
compressed check-to-variable messages are read out from R-memory module. Next,
the individual messages
accumulate
recovered by the data distributor are sent to K VPUs to
via the path indicated by the solid line. At the end of this phase, the
final summations of check-tovariable messages corresponding to all columns of the H
matrix are accumulated in the K S-memory modules.
Assuming that 6-bit quantization is used, the required memories are summarized in
the Table I and II, respectively. It can be seen that nearly 37% of memory is
reduced in this case.
The proposed partially parallel decoder architecture, which linearly increases the
decoding throughput with small hardware overhead. To facilitate the multiple data
accesses per clock cycle in a p –parallel architecture, the data corresponding to p
adjacent rows or columns of H matrix are stored into one memory entry. In the
R-memory modules, check-to-variable messages corresponding to p adjacent rows are
stored in one memory entry. Similarly, in one entry of S-memory (I-memory)
modules, summations of the check-to-variable message(intrinsic messages)
corresponding to p adjacent columns are stored.
5/10~5/16

Survey paper about H-QC & QC.
Professor :
Because I will go home today and I will not attend the meeting this week.
I am sorry.