EGRE 365
Digital Systems
Quiz 1
Open Book/ Open Notes
9/26/08
NAME: _SOLUTIONS_
Note: Although it is not shown assume each VHDL
program is preceded by the header:
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
1
1. Fill in the blanks to complete the VHDL program to model the circuit shown
below.
Q(3)
Q(2)
Q(1)
Q(0)
ENTITY P1 IS PORT
(
CLK: in std_logic;
RST: in std_logic;
D: in std_logic;
Q: OUT std_logic_vector(3 downto 0)
);
END ENTITY P1;
Architecture arch of P1 is
begin
process(clk) is
variable vQ: std_logic_vector(3 downto 0) := "0000";
begin
if RST = '1' then
vQ := "0000";
elsif CLK'EVENT AND CLK = '1' then
vQ := D & vQ(3 downto 1);
end if;
Q <= vQ;
end process;
end architecture arch;
2
2. Consider the VHDL program shown below.
entity tb is end entity tb;
architecture test of tb is
SIGNAL P: std_logic := '0';
SIGNAL N1 : integer := 1;
SIGNAL N2 : integer := 2;
SIGNAL N3 : integer := 3;
begin
P <= '1' after 10 ns, '0' after 20 ns;
process(P)
begin
N2 <= N3 * N2;
N3 <= N2 - N3;
N1 <= N3 + N2;
end process;
end test;
a)
b)
c)
d)
What is the initial value of N1? ___1____
What is the initial value of N2? ___2____
What is the initial value of N3? ___3____
What is the initial value of P? ____’0’___
3. For the program in problem 2, fill in the table below with the signal values at the
specified time.
Signal
t = 1 ns
t = 11 ns
P
‘0’
‘1’
N1
5
5
N2
6
-6
N2
-1
7
Note: Using ‘ and ‘ around the ‘0’ and ‘1’ for signal P values are
not necessary here.
3
Complete, by filling in the blank lines, the VHDL program to implement the MUX
shown below.
ENTITY mux IS
PORT ( A , B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
sel : IN STD_LOGIC_vector(1 downto 0) ;
C : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END MUX ;
ARCHITECTURE arch OF MUX IS
BEGIN
PROCESS (a, b, sel
)
BEGIN
IF (sel = "00"
) THEN
c <= "00000000";
ELSIF (SEL = "01" ) THEN
c <= a;
ELSIF (sel = "10"
) THEN
c <= b;
ELSE
c <= (OTHERS => 'Z'
);
END IF ;
END PROCESS ;
END arch ;
4
5. Complete, by filling in the blank line, the VHDL program that satisfies the
following specifications: The output Y is ‘1’ if and only if all the bits of input X are
‘1’.
ENTITY P5 IS
PORT
(
X: IN std_logic_vector(3 downto 0);
Y: OUT std_logic
);
END ENTITY P5;
Architecture arch of P5 is
begin
Y <= '1' when X = "1111" else '0';
or
Y <= X(3) and X(2) and X(1) and X(0) ;
end architecture arch;
5
6. The state diagram for a certain synchronous finite state machine (FSM) that
implements a counter is shown below.
1
1
000
001
0
1
010
0
1
011
0
100
0
1
0
The counter is clocked by CLK and has a single input X. When X = 1 the FSM
counts up. When X = 0 the FSM counts down. In the architecture below, fill in each
blank with one line of VHDL code to correctly model this counter.
ENTITY Mod5_UD_CNT IS
PORT (CLK : IN STD_LOGIC;
X : IN STD_LOGIC;
Q : OUT UNSIGNED(3 downto 1)
);
END ENTITY MOD5_UD_CNT;
ARCHITECTURE arch of MOD5_UD_CNT IS
begin
process(clk)
variable cnt: unsigned(3 downto 1) := "000";
begin
if clk'event and clk = '0' then
if X = '1' and cnt /= "100" then
cnt := cnt + 1;
elsif X = '0' and cnt /= X"000" then
cnt := cnt - 1;
end if;
end if;
Q <= cnt;
end process;
END arch;
6