CAD for VLSI
Tutorial #1
VHDL - Very High Speed Integrated
Circuit (VHSIC) Hardware Description
Language
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The World Before VHDL
• Polygon pushing
• Transistor level design
• Boolean design
– One equation for each FF data input
• Schematic Design
– Allow use of blocks in addition to FFs and gates. Impractical
for large designs
• HDL Design
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VHDL
• Very High Speed Integrated Circuit Hardware Description
Language
• VHDL is a industry standard language used to describe
hardware from the abstract to the concrete level.
• Originally intended for simulation,modeling and documentation
• Later also used for synthesis
• Originally tightly connected with US DoD, but soon found its
way to non-military applications
• First standard in 1987, revised in 1993.
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VHDL Design Units
• Entity
– Specifies the interface of the system with the
environment.
• Architecture
– Description of the internal part of the system, specifies
how the inputs are transformed into outputs.
• Configuration
– used to combine a component instance to an entityarchitecture pair.
• Package
– Encapsulate elements that can be shared globally
among design units.
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Entity
Interface description :
• Defines connections (ports) that transfer information to and
from the system.
• Defines port types : IN, OUT, INOUT
• Architecture only allowed to read IN ports, or write to OUT
ports. INOUT ports can be read or written to.
e.g.
ENTITY rsff IS
PORT (set, reset : IN BIT;
q,qb : INOUT BIT);
END rsff;
Set
q
Reset
qb
RSFF
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Architecture
Implementation of the design :
• All entities have one or more architecture
• Describes the functionality of the system.
• Always connected with a specific entity
• entity ports are available as signals within the architecture
• The description can be structural or behavioral.
• Structural : Specifies which sub-components are used and how
they are connected.
• Behavioral : Specifies what the system does, describes the
outputs’ responses to the inputs’ changes.
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Architecture Structure
Declarative part:
• data types
• constants
• additional signals
("actual" signals)
• components
• ...
Definition part (after 'begin'):
• signal assignments
• processes
• component instantiations
• concurrent statements:
order not important
architecture EXAMPLE of STRUCTURE is
subtype DIGIT is integer range 0 to 9;
constant BASE: integer := 10;
signal DIGIT_A, DIGIT_B: DIGIT;
signal CARRY:
DIGIT;
begin
DIGIT_A <= 3;
SUM <= DIGIT_A + DIGIT_B;
DIGIT_B <= 7;
CARRY <= 0 when SUM < BASE else 1;
end EXAMPLE ;
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Structural Architectures
A purely structural architecture does not describe any
functionality and contains just a list of components, their
instantiation and the definition of their interconnections.
module 2
module 1
mux
module 3
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Structural Architectures-components
• In declarative part of architecture.
entity FULLADDER is
port (A,B, CARRY_IN: in bit;
SUM, CARRY: out bit);
end FULLADDER;
architecture STRUCT of FULLADDER is
signal W_SUM, W_CARRY1, W_CARRY2 : bit;
component HALFADDER
port (A, B :
in bit;
SUM, CARRY : out bit);
end component;
component ORGATE
port (A, B : in bit;
RES : out bit);
end component;
begin
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Structural Architectures- Instantiation
• Instantiation in definition part of architecture (after
'begin')
• begin
MODULE1: HALFADDER
port map( A, B, W_SUM, W_CARRY1 );
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Port Association
• Two methods of port association are available:
•
Positional port association
– e.g. port map(A,B,C,open,E);
• order is critical
– Named port association
• e.g port map:
(Sum=>S, Carry=>open, IN1=>X, IN2=>Y);
• left side: "formals"
(port names from component declaration)
• right side: "actual“ (architecture signals)
– Independent of order in component declaration
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Behavioral Architecture Examples
entity compare is
port(A,B: in std_logic_vector(7 downto 0);
EQ: out std_logic);
end compare;
architecture compare1 of compare is
begin
EQ <= '1' when (A = B) else '0';
end compare1;
entity rotate is
port( Clk, Rst, Load: in std_logic;
Data: in std_logic_vector(7 downto 0);
Q: out std_logic_vector(7 downto 0));
end rotate;
architecture rotate1 of rotate is
begin
reg: process(Rst,Clk)
variable Qreg:std_logic_vector(7 downto 0);
begin
if Rst = '1' then
--Async reset
Qreg := "00000000";
elsif (Clk = '1' and Clk'event) then
if (Load = '1') then Qreg := Data;
else Qreg:=Qreg(0) & Qreg(7 downto 1);
end if;
end if;
Q <= Qreg;
end process;
end rotate1;
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Configurations
• Used by simulator to bind component instance to entityarchitecture pair.
• All designs simulated should have configurations.
• If no instantiated components appear in architecture,
configuration is empty
Example 1: empty configuration
CONFIGURATION cfg1_rsff OF rsff is
FOR arc_rsff
END FOR;
END cfg1_rsff;
Example 2:
CONFIGURATION cfg2_rsff OF rsff is
FOR arc2_rsff
FOR U1,U2 : nand2 USE ENTITY
WORK.nand2(arc_nand2);
END FOR;
END cfg1_rsff;
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Packages
• Allow user to define elements that are not included in the
standard VHDL language.
• A collection of commonly used data types and sub-programs
used in a design.
• Packages are defined in two parts:
– package declaration : includes declaration of all elements
defined by the package.
– package body : includes the implementation of all elements
declared in the package.
• Not all packages have bodies, sometimes body not required.
PACKAGE days_package IS
TYPE day_t IS (Sunday, Monday, Tuesday, Wednesday, Thursday, Friday,
Saturday);
END days_package;
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Predefined Packages
• The most popular packages in VHDL are defined by IEEE.
• Standard : contains all basic declarations and definitions,
always included by default.
• Std_logic_1164 : contains many useful language extensions.
• Textio : Contains definitions of all operations on texts.
• To use a the std_logic_1164 package in a design unit, include
the following statements:
library IEEE;
use IEEE.std_logic_1164.all;
For the previous user defined package example use :
use WORK.days_package.all;
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Data Type
•
•
•
•
Every signal has a type
Type specifies possible values
Type has to be fixed at signal declaration...
...either in
– entity: port declaration, or in
– architecture: signal declaration
• Types have to match:
the data types on both sides of the assignment operator '
<= ' have to match
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Data Types
• Two main data types are:
• Scalar Types
– integer, real, enumerated
• e.g. type byte is range 255 downto 0;
• type colors is (red, green, yellow); - (enumerated data type)
• Composite Types
– arrays and records
• arrays : regular structures consisting of elements of
same type
• user may define his own arrays or
• use some predefined arrays e.g. bit_vector, string
• Records: values of different types
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Definition of Arrays
• Collection of signals of the same type
Predefined arrays :
• bit_vector (array of bit)
bus_A(3)
• string (array of character)
bus_A(2)
• Example:
signal bus_A : bit_vector(3 downto 0); bus_A(1)
Signal bus_B: bit_vector(0 to 3);
bus_A(0)
bus_A <= bus_B
bus_B(0)
bus_B(1)
bus_B(2)
bus_B(3)
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Types of Assignment for 'bit' Data Types
•
•
•
•
Single bit values are enclosed in '.'
Vector values are enclosed in "..."
optional base specification (default: binary)
values may be separated by underscores to improve
readability
signal BUS_A :
bit_vector (3 downto 0);
BUS_A(3) <= ‘1’;
BUS_A <= “0011”;
BUS_A<=x”C”
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Concatenation operator: &
• The concatenation operator '&' is allowed on the right side
of the signal assignment operator '<=', only.
• architecture CLASS1 of CONCAT is
signal BYTE
: bit_vector (7 downto 0);
signal A_BUS, B_BUS : bit_vector (3 downto 0);
begin
BYTE <= A_BUS & B_BUS;
end CLASS1;
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VHDL Operators
• Expression consist of operands
and operators. Following is a
list of VHDL operators:
logical
priority
not
And
or
Nand
nor
xor
Xnor
relational
=
/=
<
<=
>
>=
shift
Sll
srl
Sla
sra
rol
ror
mod
rem
**
abs
arithmetic +
-
*
/
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Signals in VHDL
• Signals carry information.
• Allow analysis of timing relationships in a VHDL system.
• Unlike variables in C, signals contain information both on current and
previous values
• Signals can have different types, e.g. bit, bit_vector(0 to 7)
• External signals : signals which connect entity to outside world (i.e.
ports of the entity).
– Have mode associated with them:
• IN mode : data can only be read from signal (port)
• OUT mode : data can only be written to signal (port)
• INOUT mode : data can be read and written to signal (port)
• Internal signals : signals which are not visible outside the architecture.
– Declared in declarative part of architecture
– Have no mode associated with them
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Signal Assignment
• Y <= (A and B) or C
-- simple assignment
• Y <= (A and B) or C after 10ns -- delayed assignment
• Y <= ‘0’ when a = b else ‘1’; -- conditional signal assignment
Write VHDL code for the schematic.
Write a statement for V,W,X and Z
A
B
V
C
W
D
E
Z
X
S
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Remarks
• Each statement represents a gate
• The order of the statements should not be important since
there is no order of the gates in the schematic.
• How does the simulator deal with this issue ?
• When is a gate (statement) evaluated ?
• What is a sensitivity list ?
• What is a process ?
• Why do we need process statements ?
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Process Statement
•
•
•
•
•
All statements in an architecture are concurrent
Process statements exist with an architecture
Process statements are concurrent
Sequential statements exist only within process statements
All statements in the process are executed when the process is
invoked
• A process consists of a sensitivity list, a declarative part and a
statement part:
name : process(sensitivity list)
declarations;
begin
statements;
end process name;
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Process Execution
• A real physical system the logic is “always active”
• Processes behave similarly, after executing last statement they
immediately go back to first statement
• Process execution is suspended by wait statements • Execution resumes when wait condition is met
Example:
process
begin
statements;
wait <condition>;
statements;
wait <condition>;
end process;
Examples of wait statements:
wait until EN=‘1’;
wait for 50ns;
wait on a,b;
- a and b are actually a
sensitivity list
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Process Execution
• All invoked processes are executed in parallel and the order in
which they appear in the code is unimportant
• All processes are invoked at the start of a simulation
• If wait condition is the first statement, execution is immediately
suspended
• If wait condition is last statement, the process is executed once
then waits till condition is met
• Sensitivity list that appear in process statement i.e.
– process(a,b,c)
– are equivalent to “wait on” statement at end of process
• Process is invoked if a signal in the sensitivity list changes its
value
• A process with no sensitivity list is re-invoked immediately after
last statement is executed
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Signals in Processes
• signals cannot be declared within a process
• signals are declared within an architecture and are recognized by
all processes
• signal assignments within a process, only take effect when
process suspends, till then all signals retain their previous
values
• all signal assignments occur concurrently
• only last assignment of a signal is effective
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Exercise 2
process (c,d)
begin
a <= 2;
b <= a + c;
a <= d + 1;
e <= a * 2;
end process;
Initially a=0, c=1, d=0 and d is updated to 2
What are the final values of a,b and e ?
Solution:
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Exercise 2
process (c,d)
begin
a <= 2;
b <= a + c;
a <= d + 1;
e <= a * 2;
end process;
Initially a=0, c=1, d=0 and d is updated to 2
What are the final values of a,b and e ?
Solution:
•The simulation starts and the process is invoked:
So a=1, b=1, e=0 c=1 and d=0
•d is updated to 2 so the process is re-invoked:
So
a=3, b=2, e=2
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Sequential Statements
• Sequential statements can only exist with a process
• if , case , for loops are examples of sequential statements
• examples:
CASE sel IS
WHEN “10” =>
a := 1;
WHEN “01” =>
a := 2;
WHEN OTHERS =>
a := 3;
END CASE;
FOR I IN 0 TO 3 LOOP
s(i) <= a(i) xor b(i);
END LOOP;
IF set = ‘1’ AND reset = ‘0’ THEN
q <= ‘0’ ;
qn <= ‘1’ ;
ELSIF set = ‘0’ AND reset = ‘1’ THEN
q <= ‘1’ ;
qn <= ‘0’ ;
ELSIF set = ‘0’ AND reset = ‘0’ THEN
q <= q ;
qn <= qn ;
ENDIF;
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Variables
• A method is needed for immediately storing temporary data
within a process
• Immediate storage done with the aid of variables - variable
assignments take effect immediately as they are sequential
statements
• Variables can only be defined with a process and are not
recognized outside the process
• Variable declaration very similar to signal declaration
– e.g variable A : bit_vector(0 to 7);
• Variable assignment done with “:=“ e.g. A := “00110011”
• Signal has 3 properties : type, value and time, variable only has
2: type and value
• Signals and variables of same type can be assigned to each other
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Variables vs. Signals
• Signal values are assigned when the process execution
is suspended.
• variable assignments take effect immediately.
• Only the last signal assignment is carried out.
• variable immediate assignment
• Signals are know in the architecture.
• Variables are known only in the process
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Variable example
•
entity PARITY is
port (DATA: in bit_vector (3 downto 0);
ODD : out bit);
end PARITY;
architecture RTL of PARITY is
begin
process (DATA)
variable TMP : bit;
begin
TMP := `0`;
for I in DATA`low to DATA`high loop
TMP := TMP xor DATA(I);
end loop;
ODD <= TMP;
end process;
end RTL;
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Asynchronous and Synchronous Processes
It is good practice to separate logic into asynchronous logic and
asynchronous logic
clk
if clock’event and clock = ‘1’ then
means : if the clock rises from ‘0’ to ‘1’ then …
if clock’event and clock = ‘0’ then
means : if the clock falls from ‘1’ to ‘0’ then
• These statements cause the creation of edge triggered flipflops during the
synthesis process
• No need to add “else” statements to the above “if” statements
• Never add other conditions to above if statements. Instead of:
if clock’event and clock = ‘1’ and EN = ‘1’ then
do:
if clock’event and clock = ‘1’ then
if EN = ‘1’ then
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Asynchronous and Synchronous Processes
ARCHITECTURE arc_shifter OF shifter IS
SIGNAL shift_val :bit4;
BEGIN
nxt: PROCESS(load, left_right, din, dout)
BEGIN
IF (load = ’1’) THEN
shift_val <= din;
ELSIF (left_right = ’0’) THEN
shift_val(2 downto 0) <= dout(3 downto 1);
shift_val(3) <= ’0’;
ELSE
shift_val(3 downto 1) <= dout(2 downto 0);
shift_val(0) <= ’0’;
END IF;
END PROCESS;
current: PROCESS
BEGIN
WAIT UNTIL clock’EVENT and clock = ’1’;
dout <= shift_val;
END PROCESS;
END arc_shifter;
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Exercise 3
• Write code for:
A
B
x
DFF
y
DFF
out
CLK
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Exercise 3
• Write code for:
process(a,b)
begin
x<= a and b;
end process;
process(clk)
begin
A
B
x
DFF
y
DFF
out
if clk’event and clk=‘1’ then
y <= x;
CLK
out <= y;
end if;
end process;
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Drivers
• Assignment of a value to a signal is performed by a driver
• One driver is created per signal per process
• If a signal is assigned a value by two different processes, two drivers
are created
• signal assignment by more than one driver may cause a contention
problem
• contention can be resolved with the aid of a “resolution function”
process(en)
begin
if en = ‘0’ then
q < = a0;
end process;
process(en)
begin
if en = ‘1’ then
q < = a1;
end process;
process(en)
begin
if en = ‘0’ then
q < = a0;
else
q < = a1;
end process;
Is there a way to solve the contention without combining the two
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processes ?
Multi-Valued Logic
• Two value logic (0 and 1) not sufficient to simulate
real systems
• Multi-value logic used : (U, X, 0, 1, Z, W, L, H)
• The std_ulogic type is defined in the std_logic_1164
package is MVL - “u” indicated that the type is
unresolved
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IEEE Standard Logic Type
• type STD_ULOGIC is (
` U `, -- uninitialized
` X `, -- strong 0 or 1 (= unknown)
` 0 `, -- strong 0
` 1 `, -- strong 1
` Z `, -- high impedance
` W `, -- weak 0 or 1 (= unknown)
` L `, -- weak 0
` H `, -- weak 1
` - `, -- don`t care);
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std_logic type
The supports the same values as the std_ulogic type
combined with resolution according to the following table
A
?
B
Z
U
X
0
1
Z
W
L
H
U
U
U
U
U
U
U
U
U
X 0 1 Z W L H
U U U U U U U
X X X X X X X
X 0 X 0 0 0 0
X X 1 1 1 1 1
X 0 1 Z W L H
X 0 1 W W W W
X 0 1 L W L W
X 0 1 H W W H
Resolved data type: possibly several drivers per signal
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