ECE 448
Lecture 9
Algorithmic State Machines
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Required reading
• S. Brown and Z. Vranesic, Fundamentals of Digital
Logic with VHDL Design
Chapter 8.10, Algorithmic State Machine
(ASM) Charts
Chapter 10.2.1, A Bit-Counting-Circuit
Chapter 10.2.2, ASM Chart Implied Timing
Information
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Algorithmic State Machine (ASM)
Charts
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Algorithmic State Machine
Algorithmic State Machine –
representation of a Finite State Machine
suitable for FSMs with a larger number of
inputs and outputs compared to FSMs
expressed using state diagrams and state
tables.
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Elements used in ASM charts (1)
State name
Output signals
or actions
(Moore type)
0 (False)
(a) State box
Condition
expression
1 (True)
(b) Decision box
Conditional outputs
or actions (Mealy type)
(c) Conditional output box
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Elements used in ASM charts (2)
• State box – represents a state.
Equivalent to a node in a state diagram or a row
in a state table.
Moore type outputs are listed inside of the box. It
is customary to write only the name of the signal
that has to be asserted in the given state, e.g., z
instead of z=1. Also, it might be useful to write an
action to be taken, e.g., Count = Count + 1, and
only later translate it to asserting a control signal
that causes a given action to take place.
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Elements used in ASM charts (3)
• Decision box – indicates that a given condition is
to be tested and the exit path is to be chosen
accordingly
The condition expression consists of one or more
inputs to the FSM.
• Conditional output box – denotes output
signals that are of the Mealy type.
The condition that determines whether such
outputs are generated is specified in the decision
box.
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Moore FSM – Example 1: State diagram
Reset
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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ASM Chart for Moore FSM – Example 1
Reset
A
0
w
1
B
0
w
1
C
z
0
ECE 448 – FPGA and ASIC Design with VHDL
w
1
9
Example 1: VHDL code (1)
USE ieee.std_logic_1164.all ;
ENTITY simple IS
PORT ( clock
resetn
w
z
END simple ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
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Example 1: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
WHEN C =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
END CASE ;
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Example 1: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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Mealy FSM – Example 2: State diagram
Reset
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
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ASM Chart for Mealy FSM – Example 2
Reset
A
0
w
1
B
z
0
ECE 448 – FPGA and ASIC Design with VHDL
w
1
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Example 2: VHDL code (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Mealy IS
PORT ( clock : IN
resetn : IN
w
: IN
z
: OUT
END Mealy ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF Mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
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Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
END CASE ;
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Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN (y = B) AND (w=‘1’) ELSE '0' ;
END Behavior ;
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Control Unit Example: Arbiter (1)
reset
g1
r1
r2
Arbiter
g2
g3
r3
clock
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Control Unit Example: Arbiter (2)
000
Reset
Idle
0xx
1xx
gnt1 g1 = 1
x0x
1xx
01x
gnt2 g2 = 1
xx0
x1x
001
gnt3 g3 = 1
xx1
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Control Unit Example: Arbiter (3)
r 1r 2 r 3
Reset
Idle
r1
r1
gnt1 g1 = 1
r1
r2
r 1r 2
gnt2 g2 = 1
r2
r3
r 1r 2 r 3
gnt3 g3 = 1
r3
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ASM Chart for Control Unit - Example 3
Reset
Idle
r1
1
gnt1
0
1
g1
r2
1
gnt2
g2
r3
0
1
0
0
r1
r2
0
1
1
gnt3
g3
ECE 448 – FPGA and ASIC Design with VHDL
0
r3
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Example 3: VHDL code (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY arbiter IS
PORT ( Clock, Resetn
r
g
END arbiter ;
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 TO 3) ;
STD_LOGIC_VECTOR(1 TO 3) ) ;
ARCHITECTURE Behavior OF arbiter IS
TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;
SIGNAL y : State_type ;
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Example 3: VHDL code (2)
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= Idle ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN Idle =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSIF r(2) = '1' THEN y <= gnt2 ;
ELSIF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt1 =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt2 =>
IF r(2) = '1' THEN y <= gnt2 ;
ELSE y <= Idle ;
END IF ;
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Example 3: VHDL code (3)
WHEN gnt3 =>
IF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
g(1) <= '1' WHEN y = gnt1 ELSE '0' ;
g(2) <= '1' WHEN y = gnt2 ELSE '0' ;
g(3) <= '1' WHEN y = gnt3 ELSE '0' ;
END Behavior ;
ECE 448 – FPGA and ASIC Design with VHDL
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Bit Counter
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Pseudo-code for the bit counter
B = 0;
while A≠0 do
if a0 = 1 then
B = B + 1;
end if;
Right-shift A;
end while ;
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ASM chart of the bit counter
Reset
S1
B 0
Load A
0
0
s
s
1
1
S2
S3
Shift right A
B B + 1
A = 0?
Done
1
0
0
a0
1
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Expected behavior of the bit counter
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Datapath of the bit counter
0
Data
log2n
n
0
LA
EA
Clock
Sin
Load
Enable
Clock
LB
EB
D
Shift
Q
D
Load
Enable Counter
Q
Clock
log2n
A
n
z
a
ECE 448 – FPGA and ASIC Design with VHDL
0
B
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ASM chart for the bit counter control circuit
Reset
S1
LB
0
0
1
s
s
1
S2
S3
Done
EA
1
z
EB
0
0
a0
1
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VHDL code of the bit counter (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY work ;
USE work.components.shiftrne ;
ENTITY bitcount IS
PORT(Clock, Resetn : IN STD_LOGIC ;
LA, s
: IN STD_LOGIC ;
Data
: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
B
: BUFFER INTEGER RANGE 0 to 8 ;
Done
: OUT STD_LOGIC ) ;
END bitcount ;
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VHDL code of the bit counter (2)
ARCHITECTURE Behavior OF bitcount IS
TYPE State_type IS ( S1, S2, S3 ) ;
SIGNAL y : State_type ;
SIGNAL A : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL z, EA, LB, EB, low : STD_LOGIC ;
BEGIN
FSM_transitions: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
y <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN S1 =>
IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>
IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>
IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;
END IF ;
END PROCESS ;
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VHDL code of the bit counter (3)
FSM_outputs: PROCESS ( y, A(0) )
BEGIN
EA <= '0' ; LB <= '0' ; EB <= '0' ; Done <= '0' ;
CASE y IS
WHEN S1 =>
LB <= '1'
WHEN S2 =>
EA <= '1' ;
IF A(0) = '1' THEN
EB <= '1' ;
ELSE
EB <= '0' ;
END IF ;
WHEN S3 =>
Done <= '1' ;
END CASE ;
END PROCESS ;
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VHDL code of the bit counter (4)
-- The datapath circuit is described below
upcount: PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
B <= 0 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF LB = '1' THEN
B <= 0 ;
ELSEIF EB = '1' THEN
B <= B + 1 ;
END IF ;
END IF;
END PROCESS;
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VHDL code of the bit counter (5)
low <= '0' ;
ShiftA: shiftrne GENERIC MAP ( N => 8 )
PORT MAP ( D => Data,
Load => LA,
Enable => EA,
Sin => low,
Clock =>Clock,
Q => A ) ;
z <= '1' WHEN A = "00000000" ELSE '0' ;
END Behavior ;
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Shift Register With Parallel Load
Load
D(3)
D(1)
D(2)
Sin
D
Q
D
D(0)
D
Q
Q
D
Q
Clock
Enable
Q(3)
ECE 448 – FPGA and ASIC Design with VHDL
Q(2)
Q(1)
Q(0)
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N-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Load
: IN
STD_LOGIC ;
Enable : IN
STD_LOGIC ;
Sin
: IN
STD_LOGIC ;
Clock
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftrne ;
N
Enable
D
Q
N
Load
Sin
shiftn
Clock
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N-bit shift register with parallel load (2)
ARCHITECTURE Behavior OF shiftrne IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1' ) THEN
IF Load = '1' THEN
Q <= D ;
ELSIF Enable = ‘1’ THEN
Genbits: FOR i IN 0 TO N-2 LOOP
Q(i) <= Q(i+1) ;
END LOOP ;
Q(N-1) <= Sin ;
N
Enable
END IF;
D
Q
END IF ;
END PROCESS ;
Load
END Behavior ;
Sin
N
shiftn
Clock
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