VHDL
revision
VHDL revision 15a
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Q1
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A clocked 4-to-2-bit encoder circuit (with synchronous reset) has
the following interfaces:
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RESET: in STD_LOGIC;
CLK: in STD_LOGIC;
D_IN: in STD_LOGIC_VECTOR(3 downto 0);
D_OUT: out STD_LOGIC_VECTOR(1 downto 0).
At each rising edge of CLK, D_OUT will depend on D_IN as
follows:
when D_IN is "0001", D_OUT will be "00" ;
when D_IN is "0010", D_OUT will be "10" ;
when D_IN is "0100", D_OUT will be "01" ;
when D_IN is "1000", D_OUT will be "11" .
Write the VHDL entity declaration and architecture of the encoder.
VHDL revision 15a
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Q2(a)Write entity declaration (b) architecture
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A traffic light controller for controlling two sets of traffic lights (red and green
lights facing pedestrians; and red, yellow, green lights facing cars and their
drivers) at a pedestrian crossing has the following input/output signals:
clk : This is an input signal. It will be connected to an external square wave
source with a 1 second period.
reset: An asynchronous reset signal.
ped_red, pet_green: Two output signals for controlling the two (red, green)
output lights facing pedestrains. When the signal is ‘1’ the corresponding light
is on, otherwise the light is off.
car_red, car_yellow, car_green: Three output signals for controlling the three
(red, yellow, green) output lights facing cars and their drivers. When the signal
is ‘1’ the corresponding light is on, otherwise the light is off.
When the asynchronous reset= ‘1’, it will enter state1; when reset = ‘0’, it
starts to change states.
The traffic light pattern is changing at a rate of one state (or one pattern) per
16 seconds, and the sequence of the states and their display patterns are as
follows:
State
Display pattern for the state
Next State
(state1) ped_green is on and car_red is on
 (state2)
(state2) ped_red is on
and car_red and car_yellow are on  (state3)
(state3) ped_red is on
and car_green is on
 (state4)
(state4) ped_red is on
and car_yellow is on
 (back to state1).
VHDL revision 15a
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Q2(b) Write VHDL
– A synchronous input std_logic signal called
“ped_request” is added to the design in (b).
This signal is connected to a button for
pedestrians to make road crossing requests.
Normally, when no one presses the button
(ped_request = ‘0’), the traffic light is changing
according to the state sequence in (b).
However, when somebody presses the button
(ped_request = ‘1’), the traffic light controller
should jump to state1 with a delayed of 8 or
less seconds.
VHDL revision 15a
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Q3
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Q3. A state machine has states A, B, C and D. It has an asynchronous
RESET, a clock signal CLK, a 1-bit synchronous input signal INX and a
2-bit output signal OUTX. The flow diagram is shown below. Write the
complete VHDL program for this design.
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INX=‘1’
INX=’0’
RESET= ‘1’
RESET
State A
OUTX
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“01”
State B
OUTX=
“11”
INX=’0’
INX=‘0’
State C
OUTX
=
“10”
INX=‘0’
VHDL revision 15a
State D
OUTX=
“00”
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Q4
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Q4. A 3-bit synchronous binary even/odd code counter has the
following specifications.
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It has a synchronous input EO and a clock signal CLK.
It has a 3-bit output (OUTX)
It has an asynchronous reset RST.
When RST is high, OUTX is reset to “000”, otherwise the counting is
as follows: When EO is high the counter is counting even codes (Hex:
0,2,4,6,0,2,…), otherwise the counter is counting odd codes (Hex:
1,3,5,7,1,3,…). When the input EO has changed, the output is
incremented once after the next clock rising edge. For example, the
current output is 2 and EO is changed from high to low, the output
after the next clock rising edge is 3, then the counter will start to
count odd codes for subsequent clock rising edges. Or, when the
current output is 5 and EO is changed from low to high, the output is
6 after the next clock rising edge, then the counter will start to count
even codes for subsequent clock rising edges, etc.
Write the VHDL program of the entity and architecture of the
counter, the use of the operator ‘+’ is not allowed.
VHDL revision 15a
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Q5
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Q5. A serial full-adder adds two bits at one time. Using two shift registers
we can shift parallel inputs to the serial adder for adding, and the results
can be converted back to parallel bits by the third shift register at the
output of the serial full-adder.
RESET
BUS_A
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Shift register
CARRY
A
BUS_B
Serial full-adder
SUM
B
Shift register
Shift register
CLOCK
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The inputs/outputs of the serial full-adder are as follows.
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Single bit inputs: A, B, RESET, CLOCK.
Single bit outputs: SUM, CARRY.
When RESET is 1, SUM and CARRY will be 0 irrespective of A, B,
CARRY and CLOCK. When RESET is 0 and after each rising edge of
CLOCK, A and B will be added according to the state of CARRY before
the rising edge of CLOCK. After adding the result will be shown at SUM
and CARRY. Write the VHDL program.
VHDL revision 15a
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a) Fill in the table. A, B should be stable at the rising edges of CLOCK.
CARRY before the rising
edge of CLOCK
Inputs
AB
Result:
SUM after the rising edge of CLOCK
Result:
CARRY after the rising edge of CLOCK
0
00
0
0
01
1
0
10
1
0
11
0
1
1
00
01
10
11
VHDL revision 15a
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