ECE 448
Lecture 6
FPGA devices
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Required reading (1)
• S. Brown and Z. Vranesic, Fundamentals of Digital
Logic with VHDL Design
Chapter 3.6.5 Field-Programmable Gate Arrays
ECE 448 – FPGA and ASIC Design with VHDL
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Required Reading (2)
• Xilinx, Inc.
Spartan-3 FPGA Introduction
• Features
• Architectural Overview
• Package Marking
Spartan-3 FPGA Functional Description
• CLB Overview,
• Block RAM Overview
• Dedicated Multipliers
• Interconnect
ECE 448 – FPGA and ASIC Design with VHDL
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World of Integrated Circuits
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
SPLD
PAL
PLA
CPLD
PML
ECE 448 – FPGA and ASIC Design with VHDL
User
Programmable
FPGA
LUT
(Look-Up Table)
MUX
Gates
4
Two competing implementation approaches
ASIC
Application Specific
Integrated Circuit
FPGA
Field Programmable
Gate Array
• designed all the way
from behavioral description
to physical layout
• no physical layout design;
design ends with
a bitstream used
to configure a device
• designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
ECE 448 – FPGA and ASIC Design with VHDL
• bought off the shelf
and reconfigured by
designers themselves
5
What is an FPGA?
Configurable
Logic
Blocks
Block RAMs
Block RAMs
I/O
Blocks
Block
RAMs
ECE 448 – FPGA and ASIC Design with VHDL
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Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes
ECE 448 – FPGA and ASIC Design with VHDL
Reconfigurability
7
Other FPGA Advantages
• Manufacturing cycle for ASIC is very costly,
lengthy and engages lots of manpower
• Mistakes not detected at design time have
large impact on development time and cost
• FPGAs are perfect for rapid prototyping of
digital circuits
• Easy upgrades like in case of software
• Unique applications
• reconfigurable computing
ECE 448 – FPGA and ASIC Design with VHDL
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Major FPGA Vendors
SRAM-based FPGAs
• Xilinx, Inc.
Share over 60% of the market
• Altera Corp.
• Atmel
• Lattice Semiconductor
Flash & antifuse FPGAs
• Actel Corp.
• Quick Logic Corp.
ECE 448 – FPGA and ASIC Design with VHDL
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Xilinx

Primary products: FPGAs and the associated CAD
software
Programmable
Logic Devices


ISE Alliance and Foundation
Series Design Software
Main headquarters in San Jose, CA
Fabless* Semiconductor and Software Company



UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}
Seiko Epson (Japan)
TSMC (Taiwan)
ECE 448 – FPGA and ASIC Design with VHDL
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Xilinx FPGA Families
• Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for
modern designs.
• High-performance families
•
•
•
•
Virtex (0.22µm)
Virtex-E, Virtex-EM (0.18µm)
Virtex-II, Virtex-II PRO (0.13µm)
Virtex-4 (0.09µm)
• Low Cost Family
•
•
•
•
Spartan/XL – derived from XC4000
Spartan-II – derived from Virtex
Spartan-IIE – derived from Virtex-E
Spartan-3
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ECE 448 – FPGA and ASIC Design with VHDL
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Spartan-3 Family General Architecture
ECE 448 – FPGA and ASIC Design with VHDL
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CLB Structure
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
CLB Structure
ECE 448 – FPGA and ASIC Design with VHDL
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CLB Slice Structure
• Each slice contains two sets of the
following:
• Four-input LUT
• Any 4-input logic function,
• or 16-bit x 1 sync RAM (SLICEM only)
• or 16-bit shift register (SLICEM only)
• Carry & Control
• Fast arithmetic logic
• Multiplier logic
• Multiplexer logic
• Storage element
•
•
•
•
Latch or flip-flop
Set and reset
True or inverted inputs
Sync. or async. control
ECE 448 – FPGA and ASIC Design with VHDL
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LUT (Look-Up Table) Functionality
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x1
x2
x3
x4
y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
LUT
y
x1 x2 x3 x4
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
• Look-Up tables
are primary
elements for
logic
implementation
• Each LUT can
implement any
function of
4 inputs
x1 x2
y
y
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5-Input Functions implemented using
two LUTs
• One CLB Slice can implement any function of 5 inputs
• Logic function is partitioned between two LUTs
• F5 multiplexer selects LUT
A4
A3
LUT
ROM
RAM
D
A2
A1
WS
DI
F5
0
F4
A4
F3
A3
F2
A2
F1
A1
BX
WS
DI
D
1
F5
GXOR
X
G
LUT
ROM
RAM
nBX
BX
1
0
ECE 448 – FPGA and ASIC Design with VHDL
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5-Input Functions implemented using two LUTs
X5 X4 X3 X2 X1
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
Y
0
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
LUT
OUT
LUT
ECE 448 – FPGA and ASIC Design with VHDL
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Distributed RAM
RAM16X1S
• CLB LUT configurable as
Distributed RAM
• A LUT equals 16x1 RAM
• Implements Single and DualPorts
• Cascade LUTs to increase
RAM size
• Synchronous write
• Synchronous/Asynchronous
read
• Accompanying flip-flops used
for synchronous read
D
WE
WCLK
A0
A1
A2
A3
=
LUT
O
RAM32X1S
D
WE
WCLK
A0
A1
A2
A3
A4
LUT
=
LUT
or
O
RAM16X2S
D0
D1
WE
WCLK
A0
A1
A2
A3
O0
O1
or
RAM16X1D
D
WE
WCLK
A0
SPO
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
ECE 448 – FPGA and ASIC Design with VHDL
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Shift Register
LUT
• Each LUT can be
configured as shift register
IN
CE
CLK
• Serial in, serial out
• Dynamically addressable
delay up to 16 cycles
• For programmable
pipeline
• Cascade for greater cycle
delays
• Use CLB flip-flops to add
depth
LUT
=
D
CE
Q
D
CE
Q
D
CE
Q
D
CE
Q
OUT
DEPTH[3:0]
ECE 448 – FPGA and ASIC Design with VHDL
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Shift Register
12 Cycles
64
Operation A
Operation B
4 Cycles
8 Cycles
64
Operation C
3 Cycles
3 Cycles
9-Cycle imbalance
• Register-rich FPGA
• Allows for addition of pipeline stages to increase
throughput
• Data paths must be balanced to keep desired
functionality
ECE 448 – FPGA and ASIC Design with VHDL
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Carry & Control Logic
COUT
YB
G4
G3
G2
G1
Y
Look-Up
O
Table
D
Carry
&
Control
Logic
S
Q
CK
EC
R
F5IN
BY
SR
XB
F4
F3
F2
F1
X
Look-Up
Table O
CIN
CLK
CE
ECE 448 – FPGA and ASIC Design with VHDL
Carry
&
Control
Logic
S
D
Q
CK
EC
R
SLICE
23
Fast Carry Logic
Each CLB contains separate
logic and routing for the fast
generation of sum & carry
signals
MSB
Carry Logic
Routing

• Increases efficiency and
performance of adders,
subtractors, accumulators,
comparators, and counters

Carry logic is independent of
normal logic and routing
resources
ECE 448 – FPGA and ASIC Design with VHDL
LSB
24
Accessing Carry Logic

All major synthesis tools can infer carry
logic for arithmetic functions
•
•
•
•
Addition (SUM <= A + B)
Subtraction (DIFF <= A - B)
Comparators (if A < B then…)
Counters (count <= count +1)
ECE 448 – FPGA and ASIC Design with VHDL
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Block RAM
(BRAM)
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Block RAM
Port B
Port A
Spartan-3
Dual-Port
Block RAM
Block RAM
• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• 4 to 104 memory blocks
• 18 kbits = 18,432 bits per block (16 k without parity bits)
• Use multiple blocks for larger memories
• Builds both single and true dual-port RAMs
ECE 448 – FPGA and ASIC Design with VHDL
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Spartan-3 Block RAM Amounts
ECE 448 – FPGA and ASIC Design with VHDL
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Positions of Block RAM Columns
ECE 448 – FPGA and ASIC Design with VHDL
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Block RAM Port Aspect Ratios
1
2
0
4
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
8+1
0
2k x (8+1)
2047
16+2
0
1023
1024 x (16+2)
16,383
ECE 448 – FPGA and ASIC Design with VHDL
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Block RAM Port Aspect Ratios
ECE 448 – FPGA and ASIC Design with VHDL
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Single-Port Block RAM
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Dual-Port Block RAM
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Dual-Port Bus Flexibility
RAMB4_S16_S8
WEA
Port A In
1K-Bit Depth
ENA
RSTA
DOA[17:0]
Port A Out
18-Bit Width
DOB[8:0]
Port B Out
9-Bit Width
CLKA
ADDRA[9:0]
DIA[17:0]
WEB
ENB
Port B In
2k-Bit Depth
RSTB
CLKB
ADDRB[10:0]
DIB[8:0]
• Each port can be configured with a different data bus
width
• Provides easy data width conversion without any
additional logic
ECE 448 – FPGA and ASIC Design with VHDL
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Two Independent Single-Port RAMs
RAMB4_S1_S1
Port A In
8K-Bit Depth
0, ADDR[12:0]
WEA
ENA
RSTA
DOA[0]
Port A Out
1-Bit Width
CLKA
ADDRA[12:0]
DIA[0]
Port B In
8K-Bit Depth
1, ADDR[12:0]
WEB
ENB
RSTB
DOB[0]
Port B Out
1-Bit Width
CLKB
ADDRB[12:0]
DIB[0]
•
Added advantage of True DualPort
•
•
No wasted RAM Bits
Can split a Dual-Port 16K RAM into
two Single-Port 8K RAM
•
Simultaneous independent access
to each RAM
ECE 448 – FPGA and ASIC Design with VHDL
• To access the lower RAM
• Tie the MSB address bit to
Logic Low
• To access the upper RAM
• Tie the MSB address bit to
Logic High
35
Block RAM Waveforms – WRITE_FIRST
ECE 448 – FPGA and ASIC Design with VHDL
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Block RAM Waveforms – READ_FIRST
ECE 448 – FPGA and ASIC Design with VHDL
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Block RAM Waveforms – NO_CHANGE
ECE 448 – FPGA and ASIC Design with VHDL
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Embedded Multipliers
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
18 x 18 Embedded Multiplier
• Fast arithmetic functions
• Optimized to implement
multiply / accumulate modules
18 x 18 signed multiplier
Fully combinational
Optional registers with CE & RST (pipeline)
Independent from adjacent block RAM
ECE 448 – FPGA and ASIC Design with VHDL
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18 x 18 Multiplier
• Embedded 18-bit x 18-bit multiplier
• 2’s complement signed operation
• Multipliers are organized in columns
Data_A
(18 bits)
18 x 18
Multiplier
Output
(36 bits)
Data_B
(18 bits)
ECE 448 – FPGA and ASIC Design with VHDL
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Positions of Multipliers
ECE 448 – FPGA and ASIC Design with VHDL
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Asynchronous 18-bit Multiplier
ECE 448 – FPGA and ASIC Design with VHDL
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18-bit Multiplier with Register
ECE 448 – FPGA and ASIC Design with VHDL
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Input/Output Blocks
(IOBs)
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Basic I/O Block Structure
D Q
EC
Three-State
FF Enable
Clock
SR
Three-State
Control
Set/Reset
D Q
EC
Output
FF Enable
Output Path
SR
Direct Input
FF Enable
Registered
Input
Q
D
EC
Input Path
SR
ECE 448 – FPGA and ASIC Design with VHDL
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IOB Functionality
• IOB provides interface between the
package pins and CLBs
• Each IOB can work as uni- or bi-directional
I/O
• Outputs can be forced into High Impedance
• Inputs and outputs can be registered
• advised for high-performance I/O
• Inputs can be delayed
ECE 448 – FPGA and ASIC Design with VHDL
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Routing Resources
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Routing Resources
CLB
CLB
PSM
CLB
PSM
CLB
PSM
CLB
CLB
CLB
Programmable
Switch
Matrix
PSM
CLB
ECE 448 – FPGA and ASIC Design with VHDL
CLB
49
Long and Hex Lines
ECE 448 – FPGA and ASIC Design with VHDL
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Double and Direct Lines
ECE 448 – FPGA and ASIC Design with VHDL
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Spartan-3 Family Attributes
ECE 448 – FPGA and ASIC Design with VHDL
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Spartan-3 FPGA Family Members
ECE 448 – FPGA and ASIC Design with VHDL
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FPGA Nomenclature
ECE 448 – FPGA and ASIC Design with VHDL
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Device Part Marking
We’re Using: XC3S100-4FG256
ECE 448 – FPGA and ASIC Design with VHDL
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