ECE 448
Lecture 12
High Level Language (HLL)
Design Methodology
Handel C
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Main sources
• Celoxica Ltd.
Handel-C Language Reference Manual
available on WebCT
ECE 448 – FPGA and ASIC Design with VHDL
2
Behavioral Synthesis
ECE 448 – FPGA and ASIC Design with VHDL
3
Behavioral Synthesis
I/O
Behavior
Target
Library
Algorithm
Behavioral
Synthesis
RTL
Design
Logic
Synthesis
Classic RTL
Design Flow
Gate level
Netlist
ECE 448 – FPGA and ASIC Design with VHDL
4
Need for High-Level Design
•
•
•
•
•
•
Higher level of abstraction
Modeling complex designs
Reduce design efforts
Fast turnaround time
Technology independence
Ease of HW/SW partitioning
ECE 448 – FPGA and ASIC Design with VHDL
5
Advantages of Behavioral Synthesis
•
•
•
•
•
•
Easy to model higher level of complexities
Smaller in size source compared to RTL code
Generates RTL much faster than manual method
Multi-cycle functionality
Loops
Memory Access
ECE 448 – FPGA and ASIC Design with VHDL
6
High-Level Languages
• C/C++-Based
• Handel C – Celoxica Ltd., UK
• Impulse C – Impulse Accelerated Technologies
• Catapult C – Impulse Accelerated Technologies
• System C – The Open SystemC Initiative
• Java-based
• Forge
• JHDL
– Xilinx
– Brigham Young University
ECE 448 – FPGA and ASIC Design with VHDL
7
Other High-Level Design Flows
• Matlab-based
• System Generator for DSP – Xilinx
• AccelChip DSP Synthesis – AccelChip
• GUI Data-Flow based
• Corefire
– Annapolis Microsystems
• RC Toolbox – DSPlogic
ECE 448 – FPGA and ASIC Design with VHDL
8
Handel C
Design Flow
ECE 448 – FPGA and ASIC Design with VHDL
9
Design Flow
Executable
Specification
Handel-C
VHDL
Synthesis
EDIF
EDIF
Place & Route
ECE 448 – FPGA and ASIC Design with VHDL
10
Handel-C/ANSI-C Comparisons
ANSI-C
ANSI-C Standard
Library
Side Effects
i.e. X = Y++
Recursion
HANDEL-C
Handel-C Standard
Library
Preprocessors
i.e. #define
Pointers
Structures
Parallelism
Channels
ANSI-C Constructs
Arrays
for, while, if, switch
Bitwise logical operators
Logical operators
Arbitrary width
variables
Enhanced bit
manipulation
Arithmetic operators
Floating Point
Functions
Signals
RAM, ROM
Interfaces
ECE 448 – FPGA and ASIC Design with VHDL
11
Variables
• Only one fundamental type for variables: int
int 5 x;
unsigned int 13 y;
• Default types
char
short
long
8 bits
16 bits
32 bits
ECE 448 – FPGA and ASIC Design with VHDL
12
Type Summary
Type
Width
char
8 bits
unsigned char
8 bits
short
16 bits
unsigned short
16 bits
long
32 bits
unsigned long
32 bits
int
Compiler
unsigned int
Compiler
int n
n bits
unsigned int n
n bits
unsigned n
n bits
ECE 448 – FPGA and ASIC Design with VHDL
13
Arrays
• Same way as in ANSI-C
int 6 x[7];
7 registers of 6 bits wide
unsigned int 6 x [4] [5] [6];
120 registers of 6 bits wide
• Index must be a compile time constant. If
random access is required, consider using
RAM or ROM
ECE 448 – FPGA and ASIC Design with VHDL
14
Internal RAMs and ROMs
• Using ram and rom keywords
ram int 6 a [43];
a RAM consisting of 43 entries of 6 bits wide
rom int 16 b [4];
a ROM consisting of 4 entries of 16 bits wide
• RAMs and ROMs are accessed the same
way that arrays are accessed in ANSI-C
• Index need not be a compile time constant
ECE 448 – FPGA and ASIC Design with VHDL
15
Restrictions on RAMs and ROMs
• RAMs and ROMs are restricted to
performing operations sequentially. Only
one element may be addressed in any
given clock cycle
ram unsigned int 8 x [4];
x [1] = x [3] + 1; illegal
if (x [0] == 0)
x [1] = 1;
illegal
ECE 448 – FPGA and ASIC Design with VHDL
16
Multi-port RAMs
static mpram Fred
{
ram <unsigned 8> ReadWrite[256];
(read/write port)
rom <unsigned 8> Read[256];
(read only port)
}
Now we can read and write in a given
clock cycle
ECE 448 – FPGA and ASIC Design with VHDL
17
Dual Port Memory
ECE 448 – FPGA and ASIC Design with VHDL
18
Handel-C Language (1)
• A subset of ANSI-C
• Sequential software style with a “par”
construct to implement parallelism
• A channel “chan” statement allows for
communication and synchronization
between parallel branches
• Level of design abstraction is above RTL
but below behavioral
ECE 448 – FPGA and ASIC Design with VHDL
19
Handel-C Language (2)
• Each assignment and delay statement take
one clock cycle
• Automatic generation of the state machine
from an algorithmic description of the circuit
in terms of parallel and sequential blocks
• Automatic scheduling of parallel and
sequential blocks, that is the code following
a group is scheduled only after that whole
group has completed
ECE 448 – FPGA and ASIC Design with VHDL
20
Parallelism
Statement
Parallel blocks
ECE 448 – FPGA and ASIC Design with VHDL
21
Channel Communication
Statement
a
Channel
ECE 448 – FPGA and ASIC Design with VHDL
b
22
Par construct - Examples
ECE 448 – FPGA and ASIC Design with VHDL
23
Par constructs - timing
ECE 448 – FPGA and ASIC Design with VHDL
24
Par construct – shift register
ECE 448 – FPGA and ASIC Design with VHDL
25
Channels
ECE 448 – FPGA and ASIC Design with VHDL
26
Channel Communication
• Reading from a channel
Channel ? Variable;
• Writing to a channel
Channel ! Expression;
• No simultaneous write to or read from a single
channel
par
{
out ! 3;
out ! 4;
}
ECE 448 – FPGA and ASIC Design with VHDL
par
{
in ? x;
in ? y;
}
27
Scope and Variable Sharing
int w;
void main(void)
{
int x;
{
int y;
…..
}
{
int z;
…..
}
}
y
x
w
z
ECE 448 – FPGA and ASIC Design with VHDL
28
Statements
Statement
Expansion
Variable ++;
Variable = Variable + 1;
Variable --;
Variable = Variable – 1;
++ Variable;
Variable = Variable + 1;
-- Variable;
Variable = Variable – 1;
Variable += Expression;
Variable = Variable + Expression;
Variable -= Expression;
Variable = Variable – Expression;
Variable *= Expression;
Variable = Variable * Expression;
Variable <<= Constant;
Variable = Variable << Constant;
Variable >>= Constant;
Variable = Variable >> Constant;
Variable &= Expression;
Variable = Variable & Expression;
Variable |= Expression;
Variable = Variable | Expression;
Variable ^= Expression;
Variable = Variable ^ Expression;
ECE 448 – FPGA and ASIC Design with VHDL
29
Bit Manipulation Operators
Operator
<<
>>
<\\
@
[]
Width (Expression)
ECE 448 – FPGA and ASIC Design with VHDL
Meaning
Shift left
Shift right
Take least significant bits
Drop least significant bits
Concatenate bits
Bit selection
Width of expression
30
Handel-C Example
x[n]
void polyphase() {
ram int IN_WIDTH pin0_0[2], pin0_1[2], pin0_2[2], pin0_3[2];
G0(z)
32
G1(z)
32
G31(z)
z-1
ram int IN_WIDTH pin1_0[2], pin1_1[2], pin1_2[2], pin1_3[2];
ram int IN_WIDTH pin2_0[2], pin2_1[2], pin2_2[2], pin2_3[2];
32
z-1
…..
z-1
while (1) {
par {
padd0_0[half] = (pmult0_0[half][15] @ (pmult0_0[half] \\ 7)) + (pmult0_1[half][15] @ (pmult0_1[half] \\ 7));
padd0_1[half] = (pmult0_2[half][15] @ (pmult0_2[half] \\ 7)) + (pmult0_3[half][15] @ (pmult0_3[half] \\ 7));
pmult0_0[half] = 0;
pmult0_1[half] = -7 * (pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @
pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half]);
pmult0_2[half] = 109 * (pin0_2[half][7] @ pin0_2[half][7] @ pin0_2[half][7] @ pin0_2[half][7] @
if (half) {
par {
output[0] ! (((padd0_0[1][9] @ padd0_0[1]) + (padd0_1[1][9] @ padd0_1[1])) \\ 3);
ECE 448 – FPGA and ASIC Design with VHDL
31
Take/drop operators
ECE 448 – FPGA and ASIC Design with VHDL
32
Concatenation
ECE 448 – FPGA and ASIC Design with VHDL
33
Bit selection
ECE 448 – FPGA and ASIC Design with VHDL
34
Bit selection
ECE 448 – FPGA and ASIC Design with VHDL
35
Width operator
ECE 448 – FPGA and ASIC Design with VHDL
36
Arithmetic Operators
Operator
+
*
ECE 448 – FPGA and ASIC Design with VHDL
Meaning
Addition
Subtraction
Multiplication
37
Relational Operators
Operator
==
!=
<
>
<=
>=
ECE 448 – FPGA and ASIC Design with VHDL
Meaning
Equal
Not equal
Less than
Greater than
Less than or equal
Greater than or equal
38
Relational Logical Operators
Operator
&&
||
!
ECE 448 – FPGA and ASIC Design with VHDL
Meaning
Logical AND
Logical OR
Logical NOT
39
Bitwise Logical Operators
Operator
&
|
^
~
ECE 448 – FPGA and ASIC Design with VHDL
Meaning
Bitwise AND
Bitwise OR
Bitwise XOR
Bitwise NOT
40
Compile Time Constant Expressions
Operator
/
%
ECE 448 – FPGA and ASIC Design with VHDL
Meaning
Division
Modulo arithmetic
41
Width of results (1)
ECE 448 – FPGA and ASIC Design with VHDL
42
Width of results (2)
ECE 448 – FPGA and ASIC Design with VHDL
43
Example - Accumulator
void main(void)
{
unsigned int 16 sum;
unsigned int 8 data;
chanin input;
chanout output;
sum = 0;
do
{
input ? data;
sum = sum + (0 @ data);
} while (data!=0);
output ! sum;
}
ECE 448 – FPGA and ASIC Design with VHDL
44
Handel C vs. C - functions
Functions may not be called recursively, since all logic must be
expanded at compile-time to generate hardware
You can only call functions in expression statements.
These statements must not contain any other calls or assignments.
Variable length parameter lists are not supported.
Old-style ANSI-C function declarations
(where the type of the parameters is not specified) are not supported.
main() functions take no arguments and return no values.
Each main() function is associated with a clock.
If you have more than one main() function in the same source file,
they must all use the same clock.
ECE 448 – FPGA and ASIC Design with VHDL
45
Handel-C Overview
• High-level language based on ISO/ANSI-C for the implementation of
algorithms in hardware
• Allows software engineers to design hardware without retraining
• Clean extensions for hardware design including flexible data widths,
parallelism and communications
• Based on Communicating Sequential Process model
• Independent parallel processes
• “par” construct to specify parallel computation blocks within a
process
• Well defined timing model
• Each statement takes a single clock cycle
• Includes extended operators for bit manipulation, and high-level
mathematical macros (including floating point)
ECE 448 – FPGA and ASIC Design with VHDL
46
Handel C
Additional Features
ECE 448 – FPGA and ASIC Design with VHDL
47
Prialt statement
ECE 448 – FPGA and ASIC Design with VHDL
48
Restrictions on using Prialt statement
ECE 448 – FPGA and ASIC Design with VHDL
49
Macros and Functions
ECE 448 – FPGA and ASIC Design with VHDL
50
Call by reference or value
ECE 448 – FPGA and ASIC Design with VHDL
51
Call by reference or value
ECE 448 – FPGA and ASIC Design with VHDL
52
Handel-C in VHDL (1)
component handelc_component
port (
clk
: in std_logic;
sent_value : in unsigned (3 downto 0);
return_val : out unsigned (3 downto 0);
);
end component;
ECE 448 – FPGA and ASIC Design with VHDL
53
Handel-C in VHDL (2)
unsigned 4 x;
interface port_in (unsigned 1 clk with {clockport=1}) ClockPort ();
interface port_in (unsigned 4 sent_value) InPort ();
interface port_out () OutPort (unsigned 4 return_value = x);
set clock = internal ClockPort.clk;
void main(void)
{
unsigned 4 y;
y = InPort.sent_value;
x = y;
}
ECE 448 – FPGA and ASIC Design with VHDL
// Read from top-level VHDL
// Write to top-level VHDL
54
VHDL in Handel-C (1)
ENTITY parmult IS
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(7 downto 0);
b: IN std_logic_VECTOR(7 downto 0);
q: OUT std_logic_VECTOR(15 downto 0));
END parmult;
interface parmult (unsigned 16 q) parmult_instance
(unsigned 1 clk, unsigned 8 a, unsigned 2 b) with
{busformat = "B(I)"};
ECE 448 – FPGA and ASIC Design with VHDL
55
VHDL in Handel-C (2)
unsigned
unsigned
8
x1, x2;
resultX;
interface parmult
(unsigned 16 q)
parmult_instance1
(unsigned 1 clk =
unsigned 8 a
=
unsigned 8 b
=
with {busformat = "B(I)"};
ECE 448 – FPGA and ASIC Design with VHDL
__clock,
x1,
x2 )
56
VHDL in Handel-C (3)
while (1)
{
par
{
x1 = some_value;
x2 = some_value;
resultX = parmult_instance1.q;
}
}
ECE 448 – FPGA and ASIC Design with VHDL
57