ECE 448
Lecture 17
FPGAs – Survey of the Market
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Resources
Xcell Journal
available for FREE on line
or in the printed form @
http://www.xilinx.com/publications/xcellonline/
FPGA and Structured ASIC Journal
available for FREE by e-mail or on the web @
http://www.fpgajournal.com/
ECE 448 – FPGA and ASIC Design with VHDL
2
FPGAs – State of the Market
ECE 448 – FPGA and ASIC Design with VHDL
3
Major FPGA vendors
SRAM-based FPGAs
Xilinx Inc.
– www.xilinx.com
Altera Corp.
– www.altera.com
Atmel Corp.
– www.atmel.com
Lattice Semiconductor Corp.
– www.latticesemi.com
Antifuse and flash-based FPGAs
Actel Corp.
– www.actel.com
QuickLogic Corp. – www.quicklogic.com
ECE 448 – FPGA and ASIC Design with VHDL
4
The Programmable Marketplace
Q1 Calendar Year 2005
PLD Segment
Actel
Lattice
5% 7%
FPGA Sub-Segment
Xilinx
QuickLogic: 2%
Other: 2%
58%
33%
51%
31%
Altera
Xilinx
Altera
11%
All Others
Two dominant suppliers, indicating a maturing market
Source: Company reports
Latest information available; computed on a 4-quarter rolling basis
ECE 448 – FPGA and ASIC Design with VHDL
5
PLD Market Share
$2.1B
$2.6B
$4.1B
$2.6B
$2.3B
$2.6B
$3.1B
31%
33%
34%
32%
31%
32%
32%
20%
18%
17%
28%
24%
49%
50%
51%
2002
2003
2004
100%
Market Share (%)
80%
60%
39%
32%
40%
20%
30%
0%
Calendar year 1998
35%
1999
38%
2000
Xilinx
44%
2001
Altera
All Others
Source: Gartner Dataquest
ECE 448 – FPGA and ASIC Design with VHDL
6
A Maturing Market
• Dominated by two players, Xilinx and Altera
• With 51% and 32% share = 83% combined
• Remaining players scramble for niches
• All non-dedicated players have given up:
• Intel, T.I., Motorola, NSC, AMD, Cypress, Philips…
• Late-comers have been absorbed or failed:
• Dynachip, PlusLogic, Triscend, SiliconSpice (absorbed)
Chameleon, Quicksilver, Morphics, Adaptive Silicon (failed)
The pace of innovation is set by the leaders
ECE 448 – FPGA and ASIC Design with VHDL
7
Mainstream Requirements
• Versatility, high performance, and low cost
• Popular sub-functions @ ASIC performance
and cost
• User-friendly and capable tools
• Many available cores, helpful tech support
• Easy (partial) re-programmability
• Signal integrity on the pc-board
• Compatible I/O levels and standards
• Many size, speed, temp and package options
• Small-quantity part availability for fast
prototyping
ECE 448 – FPGA and ASIC Design with VHDL
8
FPGA families
Low-cost
Xilinx
Altera
High-performance
Spartan 3
Spartan 3E
Spartan 3A
Spartan 3AN
Spartan 3A DSP
Virtex 4 LX / SX / FX
Virtex 5 LX/LXT/SXT/FXT
Cyclone II
Cyclone III
Stratix II
Stratix II GX
Stratix III
ECE 448 – FPGA and ASIC Design with VHDL
9
Xilinx FPGA Families
• Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not
recommended for modern designs.
• Low Cost Family
• Spartan/XL – derived from XC4000
• Spartan-II – derived from Virtex
• Spartan-IIE – derived from Virtex-E
• Spartan-3, Spartan-3E, Spartan-3A
• Spartan-3AN, Spartan-3A DSP (90 nm)
• High-performance families
• Virtex (220 nm)
• Virtex-E, Virtex-EM (180 nm)
• Virtex-II, Virtex-II PRO (130 nm)
• Virtex-4 (90 nm)
• Virtex-5 (65 nm)
Source: [Xilinx Inc.]
ECE 448 – FPGA and ASIC Design with VHDL
10
Virtex 4
Source: [Xilinx, Inc.]
ECE 448 – FPGA and ASIC Design with VHDL
11
Three Virtex-4 Families
• Application-Specific Modular Block Architecture
makes it easier to create sub-families
• LX has logic, BlockRAMs, DSP-Blocks, I/O
• SX has more DSP Blocks and BlockRAMs,
less logic
• FX adds powerful system features:
• PPC, Ethernet controller, 11 Gbps
transceivers
Virtex-4 = eight ‘LX, three ‘SX, six ‘FX circuits
17 family members available in 2005
ECE 448 – FPGA and ASIC Design with VHDL
12
Covering a Wide Range
Throughput
Network Processing
Supercomputing
Scientific Processing
Arithmetic Performance
ECE 448 – FPGA and ASIC Design with VHDL
13
Prices of the most recent families of
Xilinx FPGAs
Low-cost
High-performance
Spartan 3
< $130*
Virtex II, Virtex II-Pro
< $3,000*
Spartan 3E
< $35*
Virtex 4
< $3,000*
* approximate cost of the largest device per unit for
a batch of 10,000 units
ECE 448 – FPGA and ASIC Design with VHDL
14
Virtex-5 Product Roadmap
ECE 448 – FPGA and ASIC Design with VHDL
15
WHAT’S NEW IN THE VIRTEX-5 FPGA FAMILY
ECE 448 – FPGA and ASIC Design with VHDL
16
4-bit LUTs vs. 6-bit LUTs
ECE 448 – FPGA and ASIC Design with VHDL
17
Hard IP Blocks in Virtex 5
ECE 448 – FPGA and ASIC Design with VHDL
18
Virtex-5 vs. Virtex-4 Performance
ECE 448 – FPGA and ASIC Design with VHDL
19
Virtex-5 Parallel I/O Standards
LVCMOS (3.3v, 2.5v, 1.8v, 1.5v, and 1.2v)
LVDS, Bus LVDS, Extended LVDS
LCPECL
PCI, PCI-X
HyperTransport (LDT)
HSTL (1.8v, 1.5v, Classes I, II, III, IV)
HSTL_I_12 (unidirectional only)
DIFF_HSTL_I_18, DIFF_HSTL_I_18_DCI
DIFF_HSTL_I, DIFF_HSTL_I_DCI
RSDS_25 (point-to-point)
SSTL (2.5v, 1.8v, Classes I, II)
DIFF_SSTL_I
DIFF_SSTL2_I_DCI
DIFF_SSTL18_I, DIFF_SSTL18_I_DCI
GTL, GTL+
ECE 448 – FPGA and ASIC Design with VHDL
20
Virtex-5 Serial I/O Standards
ECE 448 – FPGA and ASIC Design with VHDL
21
Bridges with Other Types of Devices
ECE 448 – FPGA and ASIC Design with VHDL
22
Shrinking Data Valid Window
ECE 448 – FPGA and ASIC Design with VHDL
23