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Hardware Connections for DAQFPGA Interface Interface for Driver / Data Acquisition Board P09311 David Howe DAQ Board • 32-pins utilized for DAQFPGA and FPGA-DAQ traffic – Right-most row of pins on J15 (as labeled on board) • Left-most row grounded per P08311’s spec’s. Since P09311’s design does not incorporate these pins, they are left disconnected, with the ability to be used in future projects Pins used for connection with FPGA DAQ Connector Pinout • Only two rows of one set of pin headers utilized by P08311 – For purpose of P09311, ground pins (odd pins) are not currently used • Even pins 2 through 48 are data lines for digital I/O interaction between DAQ board and FPGA • Even pins 50 through 64 are used for data transfer to/from analog I/O as well as control for A/D and D/A conversion on DAQ board Spartan-3 Starter Board Used Connectors • FPGA board utilized by P09311 • Expansion Connectors A1 and A2 used for I/O traffic – 2 Row x 20 pin female headers FPGA Connector Pinouts A1 A2 DLP USB-245M • USB FIFO: Reference http://www.dlpdesign.com/us b/dlp-usb245mv15.pdf • Pins 3, 10, 11, 12 connected together to provide power to the device via USB port • Pins 13-24 used for communication with FPGA 1 24 12 13 Breakout Board • Consists of 3 Major Components: – DAQ Pin Connectors – FPGA Pin Connectors – DLP-USP245M USB FIFO Adapter – See Bill of Materials for complete part information • Connections are soldered from the USB device and the DAQ connector to the FPGA connectors • Purpose of board is to provide intermediate stage between FPGA and peripheral interfaces – Allows easy FPGA disconnect for testing / programming purposes Top of Board Bottom of Board Breakout Board Pinout A2-5 A2-6 A2-7 A2 A1-18 A1-17 DLP USB-245M 1 2 3 4 5 6 7 8 9 10 11 12 HEADER 12X2 24 23 22 21 20 19 18 17 16 15 14 13 A1-16 A1-15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 A2-8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 A1-14 A1-13 A1-12 A1-11 A1-10 A1-9 A1-8 A1-7 A1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 A2-9 A2-10 A2-11 DAQ HEADER 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 A2-12 A2-13 A2-14 A2-15 A2-16 A2-17 A2-18 A2-19 A2-20 A2-21 A2-22 A2-23 A2-24 A2-25 A2-26 A2-27 A2-28 A2-29 A2-30 HEADER 32 A2-31 A2-32 A2-33 A2-34 A1-5 A1-6 Digital I/O Connector J10 • ZIF socket connected to I/O Expansion Header A1 on 2nd Spartan-3 FPGA via ribbon cable • This allows for testing of a multitude of IC’s through development on FPGA • Using a 2nd FPGA will allow for the largest degree of system flexibility A1-6 A1-8 A1-10 A1-12 A1-14 A1-16 A1-18 A1-20 A1-22 A1-24 A1-26 A1-28 A1-30 A1-32 A1-24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ZIFSOC-24x2 A1-5 A1-7 A1-9 A1-11 A1-13 A1-15 A1-17 A1-19 A1-21 A1-23 A1-25 A1-27 A1-29 A1-31 A1-33