Abstract
Image Processing is an application area which requires fast realisation of certain
computationally intensive operations and the ability for the system developer to experiment
with algorithms.
Recently, reconfigurable hardware devices in the form of Field
Programmable Gate Arrays (FPGAs) have been proposed as viable system building blocks in
the construction of high performance systems at an economical price. At present, however,
users must program FPGAs at a very low level and have a detailed knowledge of the
architecture of the device being used.
With this in mind, this thesis covers the design and realisation of an FPGA based image
processing machine and its associated high level programming model. This abstract
programming model allows an application developer to concentrate on the image processing
algorithm in hand rather than on its hardware implementation. The thesis proposes the
architecture of an 'ideal' FPGA based image processing machine. This machine is based upon
a PC host system with a PCI-bus add-on card containing Xilinx XC6200 series FPGA(s). A
high level instruction set for such a machine is developed based on earlier image processing
language research. XC6200 series FPGA configurations are developed to implement each
high level instruction. The performance of these FPGA implementations is demonstrated (by
simulation) and evaluated against other processors types such as image processing chips, DSP
chips and general purpose microprocessors.
The thesis then investigates a more sophisticated abstract machine that improves the
performance of the basic implementation while retaining the convenience of the high level
programming model. This model is based on the concept of a dynamically extensible high
level instruction set. Several performance improvement techniques are outlined and their
implementation on a XC6200 FPGA is demonstrated (by simulation) and evaluated against
other processors types.