Design Flow – Computation Flow
Computation Flow
• For both run-time
and compile-time
• For some
applications, must
iterate
2
Computation flow
 If many reconfigurations have to be
done, then some of the steps should
be reiterated according to the
application's need.
 A synchronization mechanism is
usually used between the processor
and the RD.
 Blocking access should also be
used for the memory access
between the two devices.
3
Computation flow
 Devices like the Xilinx Virtex II/II-
Pro up and the Altera Excalibur
feature one or more soft or hardmacro processors.
− The complete system can be
integrated in only one device.
 The reconfiguration process can
be:
− Full: The complete device have to
be reconfigured.
− Partial: Only part of the device is
configured while the rest keeps
running.
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Computation flow
 Full reconfiguration devices
task 2
− Function to be downloaded at run-time are
developed and stored in a database.
− No geometrical constraints restriction are
required for the function.
task 1
Task Request
Services
 Partial reconfiguration capabilities
Scheduler
Module
Database
− Modules represented as rectangular
boxes, are pre-computed and stored in a
data base.
− With relocation, the modules are assigned
to a position on the device at run-time.
task N
M1
M2
M4
M3
Placer
O.S.
T2
T1
T
N
Reconfigurable Device
5
RTR Challenges
task 2
• Management of Reconf. Device:
task 1
task N
− Usually as a part of the OS running on a
processor
 Scheduler
− Decides when a task must be executed
− Tasks in a database
− Characterized by (bbox, run time)
Scheduler
Module
Database
M1
 Placer
− Temporal placement: management of tasks at
run time
− Allocates a set of resources for the task.
− If cannot find a site, task is rejected
Task Request
Services
M2
M4
M3
Placer
O.S.
T2
• Challenges:
 Fragmentation
 Communication between new/old tasks
T1
T
N
Reconfigurable Device
6
Design Flow
Hardware/Software Partitioning
•
Implementation of a reconfigurable
system:
 a Hardware/software co-design
process:
•
Software part: (code-segment to be
executed on the processor)
 Development in a software
language with common tools
•
Hardware part: (to be executed on the
RD)
 Development in HDL
•
Interface
Interface:
 HDL or system-level languages
Software
C, C++, Java
etc ...
Hardware
VHDL, Verilog
HandelC, etc..
8
FPGA Architecture
•
FPGA architecture from CAD tools’ point of view:




N BLE’s (Basic Logic Element)
K-LUT: k-input LUT
I inputs, N outputs
Inputs and outputs fully connected to the inputs of each LUT
through MUXes
9
Design Flow for H/w Part
 Almost the same for all digital
circuit design
•
Synthesis
 Different particularly in Technology
mapping
− LUT-technology mapping
− Specific to target technology (device)
10
Design Flow for H/w Part
•
Design Entry
 Schematic Netlist
 HDL
 Waveform
 State Diagram
11
Textual or Schematic
•
Most people today use textual languages rather than schematic
 Poor use of screen space.
 Not appropriate for large designs.
 Hard tooling (parsing).
12
What is Synthesis?
•
Transformation of an
abstract description into a
more detailed description
 "+" operator is
transformed into a gate
netlist
 "if (VEC_A = VEC_B)
then"
 a comparator which
controls a multiplexer
•
Transformation depends on
several factors:
 Algorithm, constraints,
library
‫ مقايسه) به گيتهاي مشخص ي تبديل مي شوند اما‬،OR ،AND ‫عملگرهاي ساده (مثل‬
.‫ تبديل مي شوند‬tool ‫عملگرهاي پيچيده تر مثل ضرب ابتدا به ماکروسلهاي خاص آن‬
•
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Synthesizability
• Only a subset of VHDL is
synthesizable
• Different tools support different
subsets
 records?
 arrays of integers?
 clock edge detection?
 sensitivity list?
 ...
14
Synthesis
•
Compilation and optimization:
 All non-synthesizable data types and
operations  synthesizable code
 Translated into a set of Boolean equations
 Then minimized (Technology-independent
optimization)
•
Technology mapping:
 Assign functional modules to library elements.
 On FPGAs:
− Mapping control logic and datapath to LUTs and BLEs
− Mapping optimized datapath to on-chip dedicated
circuit structures (e.g. on-chip multipliers, adders with
dedicated carry-chains, embedded memory blocks)
 Technology-dependent optimization
15
Synthesis
•
Result:
 Netlist: a list of components and their
interconnections.
•
Netlist Formats:
 EDIF (Electronic Design Interchange Format).
 Vendor specific formats.
− Example: XNF (Xilinx Netlist Format)
16
Physical Design: Place and Route
•
Place:
 Assign locations to the components
 In hierarchical architectures:
− May need a separate clustering step: to group BLEs into
logic blocks
− Clustering: prior to placement or during placement
•
Route:
 Provide communication paths to the
interconnections.
•
Optimization problems: some cost must be minimized
•
Important factors:
 Clock frequency
 Power Consumption
 Routing congestion
 ...
17
FPGA Placement & Routing
18
Field Programmable Gate Array (FPGA)
19
Configuration Bitstream
•
Bitstream:
 LUT contents,
 Multiplexer control lines,
 Interconnections,
 ….
20
‫‪Design Flow‬‬
‫• ‪ Debug‬طرح مانند سيکل برنامه نويس ي‪:‬‬
‫کامپايل‬
‫اجرا‬
‫برنامه نويس ي‬
‫ويرايش‬
‫شبيه سازي‬
‫ويرايش‬
‫‪21‬‬
‫سنتز‬
‫شبيه سازي‬
‫کامپايل‬
‫ويرايش‬
‫ورود طرح‬
FPGA Design Flow – Example
•
Design:
 Modulo 10-counter
•
Target device:
 FPGA with 2x2 Logic Blocks (LB)
 LBs:
− Two 2-inputs LUTs
− Two edge-triggered T-Flipflops
•
Objectives:
 Area
 Latency
22
FPGA Design Flow – Example
•
Truth table:
 State transitions
•
Synthesis and Optimization:
 Karnaugh maps
 TFF inputs
23
FPGA Design Flow – Example
24
FPGA Design Flow – Example
25
References
 [Bobda07] C. Bobda, “Introduction to Reconfigurable
Computing: Architectures, Algorithms and
Applications,” Springer, 2007.
26