Ashley Good
David Graziano
Tim Meyer
Ben Petersen
Matt Saladin
NES FPGA EMULATION SYSTEM
Advisors
Joseph Zambreno
Phillip Jones
Project Plan
 Design and implement the original Nintendo
Entertainment System (NES) in reconfigurable
hardware
 FPGA: Xilinx ML-507
 Xilinx development environment
 Develop the individual NES components in VHDL
System Control
CPU
Memory
PPU
ROM
Interface
Controller Polling
VGA
Audio
Clock Generation
Central Processing Unit
 CPU
components are
completed and
integrated
 ALU
 IFID
 Branch Logic
Central Processing Unit
 Testing Plan
 Tested
 ALU
 Instruction fetch/decode
 CPU as a whole needs to be integrated and tested
with ROM file as input
 After CPU is fully tested, it will need to be
integrated with the PPU and retested
Picture Processing Unit
Picture Processing Unit
Picture Processing Unit
Picture Processing Unit
Things to be done
 Integrate components
 Controller interface
 Test in Modelsim
 Connecting to FPGA
 Test on FPGA
board
 Accessing controllers
from I/O pins on board
 VGA output
 From test program
 From NES
 Reading a game file
store on CompactFlash
card
Semester Plan and Schedule
 2/25: Have the CPU and PPU completed and







tested
3/8: Full NES Modelsim testing
3/15: VGA output from FPGA
3/15: Controller Interface
3/15: Start on board testing
4/15: On board/full system testing
4/15: Poster
4/29: Design Report