Low Power III-V InGaAs MOSFETs Featuring
InP Recessed Source/Drain Spacers
with Ion=120 μA/μm at Ioff=1 nA/μm and
VDS=0.5 V
C. Y. Huang1, S. Lee1, V. Chobpattana2, S.
Stemmer2, A. C. Gossard1,2, B. Thibeault1, W.
Mitchell1 and M. J. W. Rodwell1
1Electrical
and Computer Engineering
2Materials Department
University of California, Santa Barbara
IEDM 2014
San Francisco, CA, USA
Outline
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Problem: III-V MOSFETs are very leaky
Gate-last Process Flow
Knob 1: Wide band-gap barrier
Knob 2: Source/Drain vertical spacer
Knob 3: Ultrathin channel
Knob 4: Recessed InP S/D spacer
Knob 5: Doping-graded InP spacer
Summary
2
InGaAs/InAs FETs are leaky!
• III-V channel: low electron effective mass, high velocity,
high mobility higher current at lower VDD 
• Low band gap band-to band tunneling (BTBT) 
• High permittivity worse electrostatics, large DIBL 
Current Density (mA/m)
• Goal: reduce leakage current for low power logic!
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
VDS=0.5 V
VDS=0.05 V
40 nm
70 nm
90 nm
-0.2
0.0
0.2
0.4
0.6
Gate Bias (V)
S. Lee et al., VLSI 2013
3
UCSB Gate Last Process Flow
4
Knob 1: Wide Band-gap Barrier
 Wide band-gap barriers or Pdoped back barriers reduces
bottom leakage path.
 Solution 1: AlAsSb barriers
(Sample B) reduces
subthreshold leakage.
 Solution 2: P-doped InAlAs
barriers also work well.
Ti/Pd/
Au
Ti/Pd/
Au
Ni/Au
50 nm
N+ InGaAs
50 nm
N+ InGaAs
10 nm InGaAs N.I.D channel
3 nm AlAsSb N.I.D spacer
3 nm Si-doped InAlAs
25 nm AlAsSb N.I.D barrier
375 nm InAlAs N.I.D buffer
Semi-insulating InP substrate
C. Y. Huang et al., APL., 103, 203502 (2013) 5
Knob 2: Source/Drain Vertical Spacer
Gate
Source
Spacer
Drain
Spacer
Channel
Barrier
Substrate
Spacer
S. Lee et al., APL 103, 233503 (2013)
C. Y. Huang et al., DRC 2014.
Vertical spacers reduce the peak electric field, improve electrostatics,
and reduce BTBT floor.
6
Knob 3: Ultra-thin channel
1
Lg = 25 nm
gm (mS/m)
Current Density (mA/m)
3.0
10
I
=
500

A/

m
at
I
=100
nA/

m
on
off
0
10 and V =0.5V
2.5
D
-1
10 SS~ 72 mV/dec.
2.0
-2
10 SS~ 77 mV/dec.
-3
1.5
10
-4
10
1.0
-5
10
0.5
-6
10
-7
10 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.50.0
Gate Bias (V)
Ion (mA/m)
S. Lee et al., VLSI 2014
0.50
VDS = 0.5 V
0.45
Ioff=100 nA/m
0.40
0.35
0.30
0.25
0.20
0.15
0.10
10
S. Lee, VLSI 2014
J. Lin, IEDM 2013
T. Kim, IEDM 2013
Intel, IEDM 2009
J. Gu, IEDM 2012
D. Kim, IEDM 2012
100
Gate Length (nm)
7
Increasing band gap: In0.53Ga0.47As channel
Spacer
E2
E2
E1
E1
-4
1.2
10
-5
10
-6
10
-7
10
0.8
VDS = 0.1 V (solid)
-8
10
-9
10
0.4
0.5 V (dash)
-0.2
0.0
0.2
VGS (V)
0.4
0.6
0.0
ID, |IG| (mA/m)
2.0
1.6
Tch
1
2.4
gm (mS/m)
IDS (mA/m)
1
10
0 Sample A: black
10 Sample B: red
-1
10 Lg=22 nm
-2
10
-3
10
10
0 VDS = 0.1 to 0.7 V
10
-1 0.2 V increment
10
Sample B
-2
10 L ~22 nm
g
-3
10
I
-4
10
-5
10
-6
10
-7
10
D
BTBT
limited
|IG|
-8
10
-9
10
-0.4 -0.2 0.0 0.2 0.4 0.6
VGS (V)
Reducing channel thickness improves electrostatics,
increases confinement bandgap and reduces BTBT.
8
E-field and BTBT contour
R. Chu et al., EDL 29, 974 (2008)
J. Lin et al., EDL 35, 1203 (2014)
 Concentrated electric field at the drain end of the
channel next to the gate edge.
 Solution:
Replace InGaAs with wide band-gap InP (Eg~1.35 eV)
9
Knob 4: Recessed InP S/D spacer
12 nm InGaAs spacer
Ti/Pd/Au
5 nm Recessed InP spacer
Ti/Pd/Au
Ti/Pd/Au
Ni/Au
Ni/Au
50 nm N+InGaAs
50 nm N+InGaAs
10 nm U.I.D InGaAs
1.5 nm InGaAs
10 nm U.I.D InGaAs
1.5 nm InGaAs
ZrO2
50 nm N+InGaAs
ID, |IG| (mA/m)
1.6
1.2
0.8
0.4
0.0
1
10
0 V
= 0.1 to 0.7 V, 0.2 V step
DS
10
-1 SS ~ 77.8 mV
10 SS ~ 75.2 mV
-2
10
-3
ID
10
-4
10
-5
10
|IG|
-6
10
-7
10
-8
10
-9
10
Lg-60 nm
-0.2
0.0
0.2
0.4
0.6
2.4
2.0
1.6
gm (mS/m)
0.6
2.0
gm (mS/m)
VGS (V)
0.4
2.4
10 nm
nm N+InP
N+InP
10
5 nm U.I.D InP
3 nm
ID, |IG| (mA/m)
1
0.2
ZrO2
5 nm U.I.D InP
4.5 nm InGaAs
Back Barrier
10
0 VDS = 0.1 to 0.7 V, 0.2 V step
10
-1 SS ~ 80.1 mV
10 SS ~ 72.5 mV
-2
10
-3
ID
10
-4
10
-5
10
-6
10
|IG|
-7
10
-8
10
-9
10
0.0
50 nm N+InGaAs
10 nm N+InP
4.5 nm InGaAs
Back Barrier
-0.2
Ti/Pd/Au
Ni/Au
1.2
0.8
0.4
0.0
VGS (V)
10
InP spacer thickness: subthreshold
400
0.0
0.2
VGS (V)
0.4
0.6
SSmin (mV/dec)
ID (mA/m)
-0.2
DIBL (mV/V)
1
10
0 5 nm InP spacer
10
-1
10
-2
10
-3
10
-4
10
VDS=0.1V, Lg-28 nm
-5
VDS=0.5V, Lg-28 nm
10
-6
VDS=0.1V, Lg-45 nm
10
VDS=0.5V, Lg-45 nm
-7
10
VDS=0.1V, Lg-60 nm
-8
10
VDS=0.5V, Lg-60 nm
-9
10
300
5 nm InP spacer
13 nm InP spacer
200
Vth at 1 A/m
100
0
0.01
0.1
Gate length (m)
1
150
5 nm InP spacer
13 nm InP spacer
120
VDS = 0.5 V
90
60
0.01
0.1
Gate length (m)
1
 Minimum spacer thickness is required to maintain good
electrostatics.
 Thicker spacer is desired at drain to smooth electric field.
11
Ni/Au
50 nm N+InGaAs
1.2
13 nm U.I.D InP
4.5 nm InGaAs
Back Barrier
5 nm InP spacer
13 nm InP spacer
0.02
0.04
0.06
0.08
0.10
500
400
300
100
0
5 nm InP spacer, RS/D~199 m
13 nm InP spacer, RS/D~364 m
0.02
0.04
0.06
10 nm
nm N+InP
N+InP
10
13 nm U.I.D InP
3 nm
1.0
Gate length (m)
200
ZrO2
0.08
Gate length (m)
0.10
InGaAs
Channel
0.5
0.0
Fermi level
-0.5
-1.0
N+InGaAs
Source
N+InP
0.0
50 nm N+InGaAs
10 nm N+InP
0.8
0.4
Ti/Pd/Au
Ni/Au
Barrier
1.6
600
Ron (m)
Ti/Pd/Au
VDS = 0.5 V
Spacer
2.0
Energy (eV)
Peak gm (mS/m)
InP spacer thickness: on-state
-1.5
-2.0
0
20
40
60
80
Distance to source contact (nm)
 Thicker InP spacer increases Ron, and degrades Gm
 Thinner spacer is desired at source to reduce RS/D.
12
Knob 5: Doping-graded InP spacer
Ti/Pd/Au
Ni/Au
Ni/Au
50 nm N+InGaAs
50 nm N+InGaAs
10 nm N+InP
10 nm N+InP
8 nm doping-graded InP
8 nm doping graded InP
5 nm U.I.D InP
5 nm U.I.D InP
4.5 nm InGaAs
5 nm InAlAs U.I.D. spacer
2 nm 1E19 cm-3 N+InAlAs
100 nm InAlAs U.I.D. buffer
250 nm 1E17 cm-3 P-InAlAs
50 nm InAlAs U.I.D buffer
3 nm
S.I. InP substrate
Ron at
zero Lg
(Ω∙μm)
5 nm
UID InP
13 nm
UID InP
Doping
graded InP
~199
~364
~270
L -30 nm, 30Å ZrO2
-0.2
0.0
0.2
2.4
2.0
1.6
gm (mS/m)
ZrO2
1
g
10
0 VDS = 0.1 to 0.7 V
10
-1 0.2 V increment
10
-2
10
-3
ID
10
-4
10
-5
10
-6
|IG|
10
-7
10
-8
10
-9
10
ID, |IG| (mA/m)
Ti/Pd/Au
1.2
0.8
0.4
0.4
0.6
0.0
VGS (V)
 Doping-graded InP spacer reduces parasitic source/drain
resistance and improves Gm.
 Gate leakage limits Ioff~300 pA/μm.
13
Doping-graded InP spacer+Thicker oxide
InP graded spacer
2.0
ID, |IG| (mA/m)
0.0
VGS (V)
10
= 0.1 to 0.7 V
0 V
DS
10
1.6
-1
gm (mS/m)
-0.6 -0.3
2.4
1.2
0.6
2.0
0.2 V increment
1.6
-4
0.4
10
-5
10
-6
10
-7
10
0.0
10
-9
10
0.8
0.3
10
-2
10
-3
10
2.4
gm (mS/m)
10
= 0.1 to 0.7 V
0 V
10 DS
-1 0.2 V increment
10
-2
10 38Å ZrO2
-3
10
ID
-4
10
-5
10 60 pA/μm
-6
10
-7
10
|IG|
-8
10
-9
10
InGaAs spacer
1
ID (mA/m)
1
1.2
0.8
0.4
-8
-0.2
0.0
0.2
0.4
0.6
0.0
VGS (V)
• Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm
• 100:1 smaller Ioff compared to InGaAs spacer
14
Ion vs Lg at Ioff = 1 nA/μm
200
InGaAs spacer, 4.5 nm channel
InGaAs spacer, 3 nm channel
Doping-graded InP, ZrO2~30A
Doping-graded InP, ZrO2~38A
Ion (A/m)
150
VDS = 0.5 V
Ioff = 1 nA/m
100
Ion/Ioff~1.5x105
50
0
10
100
Gate length (nm)
1000
• Peak Ion= 150 µA/µm at VDS=0.5V for Lg-45
nm devices.
15
Ion vs Lg at Ioff = 100 nA/μm
700
VDS = 0.5 V
Ion (A/m)
600
Ioff = 100 nA/m
500
400
300
This work, 4.5 nm InGaAs channel, InGaAs spacer
This work, 3 nm InGaAs channel, InGaAs spacer
This work, 4.5 nm InGaAs channel, 5 nm InP spacer
This work, 4.5 nm InGaAs channel, graded InP
spacer, 30A ZrO2
This work, 4.5 nm InGaAs channel, graded InP
spacer, 38A ZrO2
UCSB VLSI 2014, Planar, 2.7 nm InAs channel
MIT IEDM 2013, Planar, Composite channel
Sematech IEDM 2013, Trigate, In0.53GaAs channel
200
Intel IEDM 2011, Trigate, In0.53GaAs channel
100
Purdue IEDM 2012, Nanowire, In0.53GaAs channel
0
Intel IEDM 2009, Planar, In0.7GaAs channel
Teledyne IEDM 2012, Planar, In0.7GaAs channel
0
25
50
75
100
Gate length (nm)
•
•
Peak Ion= 415 µA/µm at VDS = 0.5V for this work.
Ultrathin InAs channel shows highest Ion.
16
Metal
Gate
Metal
Drain
Source
Metal
Source
Vertical Spacer
Oxide
Gate
Oxide
Metal
Drain
Vertical Spacer
Channel
Channel
Barrier
P-barrier or wide gap barrier
Substrate
Substrate
Barrier Leakage
Channel Leakage
Metal
Gate
Metal
Drain
Source
Metal
Source
Gate
Metal
Drain
Recessed InP
Vertical Spacer
Vertical Spacer Oxide
Ultra-Thin Channel (UTC)
P-barrier or wide gap barrier
P-barrier or wide gap barrier
Recessed InP
Oxide
UTC
Ion= 150 µA/µm
Substrate
at Ioff = 1 nA/µm
Ion= 500
µA/µm
Substrate
at Ioff = 100 nA/µm
17
Recessed InP source/drain spacers enable
III-V MOSFETs for low power logic.
Thank you!
• This research was supported by the SRC Non-classical CMOS Research
Center (Task 1437.009) and GLOBALFOUNDRIES(Task 2540.001).
• A portion of this work was done in the UCSB nanofabrication facility, part
of NSF funded NNIN network.
• This work was partially supported by the MRSEC Program of the National
Science Foundation under Award No. DMR 1121053.
18