EENG 2710 Chapter 4
Modular Combinational Logic
1

Chapter 4 Homework
EENG 2710 Xilinx Project 1
And
EENG 2710 VHDL Project 2
(Projects are on Instructor’s Website)
2

Basic Decoder
• Decoder: A digital circuit designed to detect the presence of a particular digital state.
• Can have one output or multiple outputs.
• Example: 2-Input NAND Gate detects the presence of ‘11’ on the inputs to generate a
‘0’ output.
3

Single-Gate Decoders
• Uses single gates (AND/NAND) and some
Inverters.
• Example: 4-Input AND detects ‘1111’ on the inputs to generate a ‘1’ output.
• Inputs are labeled D
3
, D
2
, D
1
, and D
0 the MSB (most significant bit) and D
, with D
0
3 the LSB
(least significant bit).
4

Single-Gate Decoders
D
3
D
2
D
1
D
0
Y = D
3
D
2
D
1
D
0
D
3
D
2
D
1
D
0
Y = (D
3
D
2
D
1
D
0
)’
5

Single-Gate Examples
• If the inputs to a 4-Input NAND are given as
D
1
, D
2
, D
3
, D
4
, then the NAND detects the code
0001. The output is a 0 when the code 0001 is detected.
• This type of decoder is used in Address
Decoding for a PC System Board.
6

Multiple Output Decoders
• Decoder circuit with n inputs can activate m =
2 n load circuits.
• Called a n-line-to-m-line decoder, such as a 2to-4 or a 3-to-8 decoder.
• Usually has an active low enable that enables the decoder outputs.
G
7

2-to-4 Decoder
8

3-to-8 Decoder
9

Truth Table for a 3-to-8 Decoder
G D
2
D
1
D
0
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
1 X X X 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1
        
10

74138 3-to-8 Decoder
11

74138 3-to-8 Decoder
12

Simulation
• Simulation: The verification of a digital design using a timing diagram before programming the design in a Complex Programmable Logic
Device (CPLD).
• Used to check the Output Response of a design to an Input Stimulus using a timing diagram.
13

Simulation
14

VHDL Binary Decoder
• Use select signal assignment statements constructs or conditional signal assignment
statements constructs.
15

2-to-4 Decoder VHDL Entity
• Using a select signal assignment statement:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decode3a IS
PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); g : IN STD_LOGIC y : OUT STD_LOGIC_VECTOR (3 downto 0));
END decode3;
16

Selected Signal Entity
• In the previous slide, the Entity used a STD
LOGIC Array for Inputs and Outputs.
• The Y : OUT STD_LOGIC_VECTOR(3 downto
0) is equal to Y
3
, Y
2
, Y
1
, Y
0
.
• The STD_LOGIC Data Type is similar to BIT but has added state values such as Z, X, H, and L instead of just 0 and 1.
17

Selected Signal Assignments
• Uses a VHDL Architecture construct called
WITH SELECT.
• Format is:
– WITH (signal input(s)) SELECT.
– Signal input states are used to define the output state changes.
18

2-to-4 Decoder VHDL Architecture
ARCHITECTURE decoder OF decode2to4 IS
SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);
BEGIN inputs(2) inputs (1 downto 0)
WITH inputs SELECT
<= g;
<= d; g d(1) y <= "0001" WHEN "000",
"0010" WHEN "001",
"0100" WHEN "010",
"1000" WHEN "011",
"0000" WHEN others;
END decoder;
Y(3) Y(0) d(0)
Default case
19

2-to-4 Decoder VHDL Architecture
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decode3a IS
PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); g : IN STD_LOGIC y : OUT STD_LOGIC_VECTOR (3 downto 0));
END decode3;
ARCHITECTURE decoder OF decode2to4 IS
SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);
BEGIN inputs(2) inputs (1 downto 0)
WITH inputs SELECT y <=
<= g;
<= d;
"0001" WHEN "000",
"0010" WHEN "001",
"0100" WHEN "010",
"1000" WHEN "011",
"0000" WHEN others;
END decoder;
20

Decoder Architecture
• The decoder Architecture used a SELECT to evaluate d to determine the Output y.
• Both d and y are defined as an Array (or bus or vector) Data Type.
• The last state for WHEN OTHERS is added for the other logic states (Z, X, H, L, etc.).
21

Seven-Segment Displays
• Seven-Segment Display: An array of seven independently controlled LEDs shaped like an
8 that can be used to display decimal digits.
22

Seven-Segment Displays
23

Seven-Segment Displays
24

Common Anode Display
• Common Anode Display (CA): A sevensegment display where the anodes of all the
LEDs are connected together to V
CC turns on a segment (a to g).
and a ‘0’
25

Common Cathode Display
• Common Cathode Display (CC): A sevensegment display where all the cathodes are connected and tied to ground, and a ‘1’ turns on a segment.
26

Common Cathode/Anode Display
27

Common Anode Display
28

Seven-Segment Decoder/Driver
• Receives a BCD (Binary Coded Decimal) 4-Bit input, outputs a BCD digit 0000 – 1001 (0 through 9).
• Generates Outputs (a–g) for each of the display LEDs.
• Requires a current limit series resistor for each segment.
29

Seven-Segment Decoder/Driver
• Decoders for a CC-SS have active high outputs while decoders for a CA-SS have active low outputs (a to g).
• The outputs generated for the binary input combinations of 1010 to 1111 are “don’t cares”.
• The decoder can be designed with VHDL Logic
(7447, 7448).
30

SS Decoder/Driver Truth Table
Digit D3 D2 D1 D0 a b c d e f g
0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 1 1 0 0 1 1 1 1
4
5
2
3
6
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
8
9
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
31

Decoder/Driver Entity (CA)
ENTITY bcd_7seg IS
PORT( d3, d2, d1, d0 a, b, c, d, e, f, g
END bcd_7seg;
: IN BIT;
: OUT BIT;
32

Decoder/Driver Architecture
ARCHITECTURE seven_segment OF bcd_7seg IS
SIGNAL input : BIT_VECTOR (3 downto 0);
SIGNAL output : BIT_VECTOR (6 downto 0);
BEGIN input <= d3 & d2 & d1 & d0;
-- Uses two intermediate signals called input and output (internal no pins)
-- Creates an array by using the concatenate operator (&)
In this case input(3) <= d3, input(2) <= d2, etc.
33

Decoder/Driver Architecture
WITH input SELECT output <= “0000001” WHEN “0000”,
“1001111” WHEN “0001”,
“0010010” WHEN “0010”,
“0000110“ WHEN “0011”,
• • •
• • •
• • •
“1111111” WHEN others;
34

Decoder/Driver Architecture f e g
END seven_segment c d a b
<=
<=
<=
<=
<=
<=
<= output(6); output(5); output(4); output(3); output(2); output(1); output(0);
35

SS VHDL File Description
• In the preceding example file, a concurrent select signal assignment was used (WITH
(signals) SELECT.
• The intermediate output signals were mapped to the segments (a to g).
• Example: when Input (D3 – D0) is 0001, the decoder sets a=d=e=f=g=1, b=c=0.
36

Encoders
• Encoder: A digital circuit that generates a specific code at its outputs in response to one or more active inputs.
• It is complementary in function to a decoder.
• Output codes are usually Binary or BCD.
37

Priority Encoders
• Priority Encoder: An encoder that generates a code based on the highest- priority input.
• For example, if input D
3 output is 101, not 011. D
5 than D
3 has a higher priority and the output will respond accordingly.
= input D
5
, then the
38

BCD Priority Encoder
D
9
– D
0
= 0100001111
BCD # = ?
39

BCD Priority Encoder
D
9
– D
0
= 0101001011
Q
3
– Q
0
= 1000 (8
10
)
40

BCD Priority Encoder
D
9
– D
0
= 1000000001
Q
3
– Q
0
= 1001 (9
10
)
41

BCD Priority Encoder
D
9
– D
0
= 1101001011
Q
3
– Q
0
= 1001 (9
10
)
42

1
Put It All Together
D
C
B
A
= 1
= 0
= 0
= 0
43

Priority Encoder VHDL Entity
-- hi_pri8a.vhd
ENTITY hi_pri8a IS
PORT( d q
END hi_pri8a;
: IN BIT_VECTOR (7 downto 0);
: OUT BIT_VECTOR (2 downto 0));
44

Priority Encoder VHDL Architecture
ARCHITECTURE a OF hi_pri8a IS
BEGIN
-- Concurrent Signal Assignments q(2) <= d(7) or d(6) or d(5) or d(4); q(1) <= d(7) or d(6) or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2)); q(0)
END a;
<= -- in a similar fashion
45

8 to 3 bit Encoder
46

8-to-3 Encoder Truth Table
Active High Inputs
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
  
1 0 0 0 0 0 0 0 1 1 1
47

Basic Multiplexers (MUX)
• (MUX): A digital circuit that directs one of several inputs to a single output based on the state of several select inputs.
• A MUX is called a m-to-1 MUX.
• A MUX with n select inputs will require m = 2 n data inputs (e.g., a 4-to-1 MUX requires 2 select inputs S
1 and S
0
).
48

Basic Multiplexers (MUX)
49

Basic Multiplexers (MUX)
50

4-to-1 Multiplexers Truth Table
S
1
S
0 0
0
0 1
1 0
1 1
Y
D
0
D
1
D
2
D
3
51

Multiplexer Logic
• Boolean expression for a 4-to-1 MUX is
Y

D
0
S
1
S
0

D
1
S
1
S
0

D
2
S
1
S
0

D
3
S
• This expression can be expanded to any size
1
S
0
MUX so the VHDL architecture could use a very long concurrent Boolean statement.
52

Double Subscript Notation
• Naming convention in which variables are bundled in numerically related groups, the elements of which are themselves numbered.
• The first subscript identifies the group that a variable belongs to (D
01
, D
00
).
• The second subscript indicates which element of the group a variable represents.
53

4-bit Bus MUX
54

Truth Table for a 4-to-1
4-bit Bus MUX
S
1
S
0
0 0
0 1
1 0
1 1
Y
3
Y
2
Y
1
Y
0
D
03
D
02
D
01
D
00
D
13
D
12
D
11
D
10
D
23
D
22
D
21
D
20
D
33
D
32
D
31
D
30
55

VHDL Constructs For MUXs
• The following three VHDL constructs can be used to describe the Multiplexer:
– Concurrent Signal Assignment Statement
– Select Signal Assignment Statement
– CASE Statement
56

PROCESS and Sensitivity List
• PROCESS: A VHDL construct that contains statements that are executed if a signal in its sensitivity list changes.
• Sensitivity list: A list of signals in a PROCESS statement that are monitored to determine whether the Process should be executed.
57

Case Statement
• A case statement is a VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.
58

Case VHDL Template
CASE __expression IS
WHEN __constant_value =>
__statement;
__statement;
WHEN __constant_value =>
__statement;
__statement;
WHEN OTHERS =>
__statement;
__statement;
END CASE;
59

MUX 4-to-1 VHDL – 1
• Basic Entity declaration for a 4-to-1 MUX:
ENTITY mux4case IS
PORT( s d0, d1, d2, d3 : IN BIT;
: IN BIT_VECTOR (1 downto 0); y
END mux4case;
: OUT BIT);
60

MUX 4-to-1 VHDL – 2
ARCHITECTURE mux4to1 OF mux4case IS
BEGIN
-- Monitor select inputs and execute if they change
PROCESS(s)
BEGIN
CASE s IS
61

MUX 4-to-1 VHDL – 3
WHEN "00" =>
END CASE;
END PROCESS;
END mux4to1;
WHEN "01"
WHEN "10"
=>
=>
WHEN "11" =>
WHEN others => y y y y y
<=
<=
<=
<=
<= d0; d1; d2; d3;
'0';
62

Multiplexer Applications
• Used in directing multiple data sources to a single processing element such as multiple CD
Player Streams to a DSP.
• Used in Time Division Multiplexing (TDM) by the Phone Service to multiplex multiple voice channels on a single coax line (or fiber).
63

Multiplexer Applications
Used in directing multiple data sources to a single processing element such as multiple CD Player
Streams to a DSP.
64

Multiplexer Applications
Used in Time Division Multiplexing (TDM) by the
Phone Service to multiplex multiple voice channels on a single coax line (or fiber).
65

Time Division Multiplexing (TDM)
• Each user has a specific time slot in a TDM data frame. Each frame has 24 users.
• TDM requires a time-dependent (counter) source to synchronize the select lines.
• Each user’s time slot repeats on the next frame for more data.
• The links are called T-Carriers (such as a T1
Line).
66

TDM Data Streams
• Two methods in which data is transmitted:
– Bit Multiplexing: One bit is sent at a time from the channel during the channel’s assigned time slot
– Word Multiplexing: One byte is sent at a time from the channel during the channel’s assigned time slot
67

TDM Data Streams
68

TDM Data Streams
69

Demultiplexer Basics
• Demultiplexer: A digital circuit that uses a decoder to direct a single input (from a MUX) to one of several outputs.
• A DEMUX performs the reverse operation of a
MUX.
• The selected output is chosen by the Select
Inputs (as in a MUX).
70

Demultiplexer Basics
• Designated as a 1-to-n DEMUX that requires m select inputs such that n outputs = 2 m select inputs.
• 1-to-4 DEMUX Equations:
Y
( 0 )

D
0
S
1
S
0
; Y
( 1 )

D
0
S
1
S
0
;
Y
( 2 )

D
0
S
1
S
0
; Y
( 3 )

D
0
S
1
S
0
.
• They are similar to a MUX and can be designed using CASE Statements.
71

Demultiplexer Basics
72

Demultiplexer Basics
73

Demultiplexer Basics
74

Demultiplexer VHDL Entity
ENTITY dmux8 IS
PORT( s d y
: IN STD_LOGIC_VECTOR (2 downto 0);
: IN STD_LOGIC;
: OUT STD_LOGIC_VECTOR (0 to 7));
END dmux8;
75

Demultiplexer VHDL Architecture
ARCHITECTURE a OF dmux8 IS
SIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0);
BEGIN inputs <= d & s;
WITH inputs select
Y <= “01111111” WHEN “0000”,
“10111111” WHEN “0001”,
• • •
• • •
“11111111” WHEN others;
END a;
76

Demultiplexer VHDL Architecture
77

Analog MUX/DEMUX
• Uses a CMOS Switch or Transmission Gate that will allow a signal to Pass in two directions for + and – Voltages.
• Some commercial types such as a CD4066 or 74HC4066.
• Multiplexes 4 CMOS Switches to a single output (Y) for analog multiplexing.
78

Analog MUX/DEMUX
79

Analog MUX/DEMUX
80

Magnitude Comparators
• Magnitude Comparator: A digital circuit that compares two n-Bit Binary Numbers and indicates if they are equal or which is greater.
• A very simple One-Bit Magnitude Comparator is the Two-Input XNOR Gate:
– When both inputs are equal, the output is a 1; if they are not, it is a 0.
81

A
1
B
1
A
0
B
0
2-Bit Comparator
AEQB
82

2-Bit Magnitude Comparator
A
1
B
1
A
0
B
0
AEQB
AGTB
ALTB
83

Magnitude Comparators
• Multiple Bit Comparisons
AEQB

( A n1

B n1
) • ( A n2

B n2
)

.
• Also adds A > B (AGTB) and A < B (ALTB) Outputs.
• For A > B, start with the MSB:
– If A n–1
> B n–1
, then AGTB = 1
• If not, then try the next most significant bit.
84

4-Bit Magnitude Comparator
A
3
B
3
A
2
B
2
A
1
B
1
A
B
0
0
ALTB
AEQB
AGTB
85

VHDL 4-Bit Magnitude
Comparator
ENTITY compare4 IS
PORT( a, b
15;
: IN INTEGER RANGE 0 to agtb, aeqb, altb : OUT STD_LOGIC);
END compare4;
86

VHDL 4-Bit Magnitude
Comparator
ARCHITECTURE a OF compare4 IS
SIGNAL compare :STD_LOGIC_VECTOR (2 downto 0);
BEGIN
PROCESS (a, b)
BEGIN
IF a<b THEN compare <= “110”;
ELSIF a = b THEN compare <= “101”;
87

VHDL 4-Bit Magnitude
Comparator
ELSIF a > b THEN compare <= “011”;
ELSE compare <= “111”;
END IF; agtb <= compare(2); aeqb <= compare(1); altb <= compare(0);
END PROCESS
END a;
88

Temperature Comparator
89

Parity Basics
• Parity: A digital system that checks for errors in a n-Bit Binary Number or Code.
• Even Parity: A parity system that requires the binary number and the parity bit to have an even # of 1s.
• Odd Parity: A parity system that requires the binary number and the parity bit to have an
Odd # of 1s.
90

Parity Basics
• Parity Bit: A bit appended on the end of a binary number or code to make the # of 1s odd or even depending on the type of parity in the system.
• Parity is used in transmitting and receiving data by devices in a PC called UARTs, that are on the COM
Port.
• UART = Universal asynchronous
Receiver/Transmitter
91

Parity Basics
92

Parity Calculation
• N
1
= 0110110:
– It has four 1s (an even number).
– If Parity is ODD, the Parity Bit = 1 to make it an odd number (5).
– If Parity is EVEN, the Parity Bit = 0 to keep it an even number (4).
• N
2
= 1000000:
– One 1 in the data.
– P odd
– P even
= 0.
= 1.
93

Parity Generation HW
• A basic two-bit parity generator can be constructed from a
XOR Gate.
• When the two inputs are 01 or 10, the output is a 1 (so this is even parity).
• When the two inputs are 00 or 11, the output is a 0.
• For a parity generator of n bits, add more gates.
94

Parity Generator HW
• Cascading a long chain of XOR gates could cause excessive propagation delays.
• To check for a Parity error, the receiver (R a new Parity Bit (P
X
) just generates
1
) based on the received parallel data and then compares it to the parity bit transmitted (P
2
).
95

Parity Generator HW
• If there is an error, the two bits (P
1 and P
2
) will not be equal, and we can use a two-bit magnitude comparator to check this (an XOR gate).
• This check is called syndrome.
– If there are no errors, the syndrome output (P err
) is 0.
• Parity is not a foolproof system.
– If two bits are in error, the error is not detected.
96

4-Bit Parity Generator
97

VHDL GENERATE Statement
__generate_label:
FOR __index_variable IN __range GENERATE
__statement;
__statement;
END GENERATE;
98

4-Bit Parity VHDL Code
LIBRARY ieee;
USE ieee.std_logic1164.ALL;
ENTITY parity4_gen IS
PORT( d : IN STD_LOGIC_VECTOR (0 to 3); pe ; OUT STD_LOGIC);
END parity4_gen;
99

4-Bit Parity VHDL Code
ARCHITECTURE parity OF parity4_gen IS
SIGNAL p : STD_LOGIC_VECTOR (1 to 3);
BEGIN p(1) <= d(0) xor d(1); parity_generate:
FOR i IN 2 to 3 GENERATE p(i) <= p(i-1) xor d(i);
END GENERATE; pe <= p(3);
END parity;
100

Binary Adders
• Half Adder (HA): A circuit that will add two bits and produce a sum bit and a carry bit.
• Full Adder (FA): A circuit that will add a carry bit from another HA or FA and two operand bits to produce a sum bit and a carry bit.
101

Basic HA Addition
• Binary Two-Bit Addition Rules:
0 + 0 = 00
0 + 1 = 01
1 + 1 = 10
102

HA Circuit
• Basic Equations: S = A XOR B, C = A and B where
S = Sum and C = Carry.
• Truth Table for HA Block:
103

Full Adder Basics
• Adds a C
IN input to the HA block.
• Equations are modified as follows:
C
OUT


(

( A

B
A

B
) C
IN
)

C
IN

A B
• A FA can be made from two HA blocks and an
OR Gate.
104

Full Adder Basics
105

Full Adder Basics
106

Full Adder Basics
107

Parallel Adders
• A circuit, consisting of n full adders, that will add n-bit binary numbers.
• The output consists of n sum bits and a carry bit.
• C
OUT of one full adder is connected to C
IN the next full adder.
of
108

4-Bit Parallel Adder
109

4-Bit Parallel Adder
110

Ripple Carry
• In the n-Bit Parallel Adder (FA Stages) the
Carryout is generated by the last stage (FAN).
• This is called a Ripple Carry Adder because the final carryout (Last Stage) is based on a ripple through each stage by C
IN at the LSB Stage.
111

Ripple Carry
• Each Stage will have a propagation delay on the C
Gate.
IN to C
OUT of one AND Gate and one OR
• A 4-Bit Ripple Carry Adder will then have a propagation delay on the final C
OUT
Gates.
of 4

2 = 8
• A 32-Bit adder such as in an MPU in a PC could have a delay of 64 Gates.
112

Ripple Carry
113

Look-Ahead Carry
• Fast Carry or Look-Ahead Carry:
– A combinational network that generates the final
C
OUT
B n
).
directly from the operand bits (A
1 to A n
, B
– It is independent of the operations of each FA
1 to
Stage (as the ripple carry is).
114

Look Ahead Carry
• Fast Carry has a small propagation delay compared to the ripple carry.
• The fast carry delay is 3 Gates for a 4-Bit
Adder compared to 8 for the Ripple Carry.
115

4-Bit Fast Carry Circuit
116

Subtractor (2’s Complement)
• The concept of Subtraction using 2’s
Complement addition allows a Parallel FA to be used.
• The subtract operation involves adding the inverse of the subtrahend to the minuend and then adding a 1.
117

Subtractor (2’s Complement)
• Difference

A

B

A

B

1
• This operation can be done in a parallel n-Bit FA by inverting (B
1
Stage to +5 V.
to B n
) and connecting C
IN at the LSB
• The circuit can be modified to allow either the ADD or SUBTRACT operation to be performed.
118

Subtractor (2’s Complement)
119

Parallel Binary Adder/Subtractor
• XOR gates are used as programmable inverters to pass binary numbers (e.g., B
1
B
2
B
3
B
4
) to the parallel adder in true or complemented form.
•
When ADD /SUB

1, B is complement ed.
When ADD /SUB

0, B is in its true form.
120

Parallel Binary Adder/Subtractor
1
0
X
B
Y
B
X=1
B’ B
X=0
B
121

Overflow
• If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred.
• Overflow is not possible if the sign bits of the operands are different from each other.
122

Overflow Examples
• Adding two 8-bit negative numbers:

80
80
H
H

1000
1000
0000
0000
100 H 10000 0000 (Sign bit overflow; V

1 )
• Adding two 8-bit positive numbers:

7 FH
01 H
80 H
0111 1111
0000 0001
1000 0000 (Sign bit overflow; V

1 )
123

Overflow 8-bit Parallel Adder
S
A
A
7
A
6
A
5
A
4
A
3
A
2
A
1
( S
A

Sign bit of A )
S
B
B
7
B
6
B
5
B
4
B
3
B
2
B
1
( S
B

Sign bit of B )
S

S
7
S
6
S
5
S
4
S
3
S
2
S
1
( S


Sign bit of sum)
124

Overflow Detector Truth Table
1
1
0
0
S
A
0
0
1
1
0
0
1
1
S
B
0
0
1
1
0
1
0
1
S

0
1
0
1
V

S
A
S
B
S


S
A
S
B
S

1
0
0
V
0
1
0
0
0
125

Overflow Detector
126

BCD Adder
• A Parallel Adder whose output sum is in groups of 4 bits, each representing a BCD
(8421) Digit.
• Basic design is a 4-Bit Binary Parallel Adder to generate a 4-Bit Sum of A + B.
• Sum is input to the four-bit input of a Binaryto-BCD Code Converter.
127

BCD Adder
128