UNIVERSITY OF TEHRAN
Electrical and Computer Engineering Department
ECE 517-3586 Logic Design, Test # 2
Spring Semester 1378
Week of Lecture 32 - Makeup
Computer Account #___________________
First Name :_________________________
Last Name :__________________________
Number :_____________________________

Signature :__________________________
Grade:
Problem 1. ______/20
Problem 2. ______/20
Problem 3. ______/20
Problem 4. ______/20
Problem 5. ______/20
Total: ______/100
DO NOT USE LAPTOPS
EXTRA SHEETS WILL NOT BE ACCEPTED
THIS IS A CLOSED BOOK CLOSED NOTE EXAM
YOU HAVE TWO HOURS FOR WORKING ON THIS TEST
YOU MUST SHOW COMPLETE WORK ON ALL PROBLEMS
NOT ALL FREE MAPS AND DRAWINGS ARE NECESSARILY NEEDED
 ……………………………………………………………………………………….
1
1. Show the design of a counter circuit that counts the following sequence in the right or
left directions. If the R input is 1, the count goes in the R direction. Use D-type flipflops. You will need 3 flip-flops. You need not show the complete logic diagram,
writing flip-flop input equations in boxes next to the flip-flops will suffice. Use
Karnaugh maps shown below, use abc for flip-flop outputs, a for the MSB and c for
the least. Make sure you follow the labeling shown in the maps and diagram.
000
011
110
001
111
R=1
Q
a
Q
b
Q
c
1D
C1
1D
C1
1D
C1
ab
rc
00
01
11
10
00
01
11
10
ab
rc
00
01
11
10
00
01
11
10
ab
rc
00
01
11
10
00
01
11
10
 ……………………………………………………………………………………….
2
2. A 74163 counter and a 74164 shift register are connected and initialized as shown
below. Values shown are time 0 initial values. QA is the least significant bit of the
counter output. The initial value at the counter input is 12. The two anded-inputs of
the shift-register are tied together to act as a single serial input. For the next 20 clock
pulses show the waveform on output Z and the value of the counter count output.
Show counter values in decimal. QE to QH outputs are initially 0.
A
B
X
CLK
1
CLR
74164
QA
QB
QC
QD
QE
QF
QG
QH
0
0
1
1
A
B
C
D
1
1
1
ENP
ENT
CLK
LOAD
CLR
QA
QB
QC
QD
RCO
1
1
1
1
Z
74163
X Input
Z Output
Counter
 ……………………………………………………………………………………….
3
3. This problem is on design of a Mealy state machine that continuously searches on its
x input for 1110 or 1101 sequences. If either sequence is found the circuit output, z,
becomes 1. Show the complete state diagram. Show excitation tables for
implementing this state machine using D-type flip-flops. Use Karnaugh maps shown
below. Follow map labeling shown, or you will not receive partial credit.
xa
bc
00
01
11
10
00
01
11
10
xa
bc
00
01
11
10
00
01
11
10
xa
bc
00
01
11
10
00
01
11
10
 ……………………………………………………………………………………….
4
4. In this design you are to show the complete design of an asynchronous circuit with
one input a and two outputs c1 and c0 . The two bit output keeps a modulo-3 count of
complete positive pulses that are received on the a input. For example initially the
outputs may be at 00, after a complete pulse on a, the outputs become 01 then 10 and
after the third complete positive pulse on a the outputs become 00 again, indicating
the remainder of 3 when divided by 3. A) Show the complete primitive flow table
and the flow table for this circuit. Hint: Do not try minimizing it with implication
tables. B) Make a race-free state assignment and show transition tables. C) Perform
the rest of the design steps and show a complete design.
A
C1
C0
a:
0
1
1
2
3
4
5
6
7
8
 ……………………………………………………………………………………….
5
5. A serial communication device has two serial inputs (synch and data), a clock input
(clk), an 8-bit parallel output (count), and an output named receiving. Data bits on the
inputs are synchronized with the system clock, clk. This device looks for a sequence
of 110 (we will refer to this sequence as the begin message) on its synch input and
when this is received it starts counting number of 1’s that are received on the data
input. While counting is being done and before a sequence of 011 is received on
synch (we will refer to this as an end message), the device counts the number of 1’s
received on the data input. The count output keeps the modulo-89 count of number
of 1’s that are received on this data input. While this counting continues, the
receiving output stays at 1. When an end message is received, the device goes to a
halt state and the count output stays unchanged and keeps its count value before the
last bit of the end message. In this state, the receiving output is set to zero. In the
halt state, device outputs remain unchanged while the device is searching for a new
begin message. A) Show a state diagram that detects begin and end messages on its
synch input, generates the counting output and enables the counting process. Begin
and end messages cannot overlap. Represent this state machine with a box with
appropriate inputs and outputs. B) Show a counter that can be enabled to count
synchronous number of 1’s received on its data input. Use counters shown below.
C) Show interconnection of inputs and outputs of box of Part A to the counter of Part
B.
Synch
Data
Communication
Device
Count
Receiving
Clk
[begin]
continue to count, receiving is 1
[end]
hold count output value, receiving is 0, ignore data
[begin]
...
 ……………………………………………………………………………………….
6