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SRIPERUMBUDUR, CHENNAI-631604.

**MODEL THEORY EXAM-OCTOBER2012 **

** DATE: 17.10.2012 **

**BRANCH: 2nd Year 3 rd Semester ECE DURATION: 3 Hours **

** SUBJECT: EC2203 Digital Electronics MAX. Marks: 100 **

** Part-A (Answer all questions) (10 x 2 = 20) **

1. State De-Morgan’s theorem.

2. What are open collector and totem pole outputs?

3. Implement the following function using suitable MUX F(x,y,z)=∑m(0,2,5,7).

4. Draw the gate level logic diagram of a Master Slave JK flip-flop.

5. Mention the applications of flip-flop.

6. Draw the state diagram of MOD-10 counter.

7. What is Race?

8. Which memory is called volatile?, why is it so?

9. Define static hazard. How it can be avoided?

10. Compare the features of PROM, PAL and PLA.

**Part – B (5 x 16 = 80 marks) **

11 (a)(i) Simplify the following Boolean function using 4-variable map

F(w,x,y,z) = ∑(2, 3,10, 11, 12,13,14,15) (8)

(ii) Draw a NAND logic diagram that implements the complement of the following

function F(a,b,c,d) = ∑m(0,1,2,3,4,8,9,12) (8)

(or)

(b) (i) Using Quine McCluskey method simplify the boolean expression

F(x1,x2,x3,x4) = ∑(1,3,4,5,9,10,11)+d(6,8) (16)

12 (a) Design a carry look ahead adder with necessary diagram (16)

(or)

(b) .(i) Explain the operation of a 4-bit magnitude comparator circuit (16)

13 (a) Design a 3-bit binary counter using T-flip-flop that has a repeated sequence of six state

000-001-010-100-101-110. Give the state table,state diagram and logic diagram. (16)

(or)

(b) (i) Construct a counter circuit and write a HDL program module for the same. (16)

14 (a) (i) Write a short notes on FPGA (6)

(ii) Implement the following two boolean function with a PLA

F1(A,B,C)=∑m(0,1,2,4), F2(A,B,C)=∑m(0,5,6,7)

(10)

(or)

(b) (i) Design a combinational circuit using ROM. The circuit accepts a three bit

number and output a binary number equal to the square of the input number (10)

(ii) Write a short notes on RAM with a neat sketch (6)

15 (a) Develop the state diagram and primitive flow table for a logic system that has 2 inputs, x and y and an output z. And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y=0 then z=1, whenever x=0 and y=1 then z=0.

When x=y=0 or x=y=1 no change in z, it remains in the previous state. The logic system has edge triggered inputs without having a clock. The logic system changes state on the rising edges of the 2 inputs.Static input values are not to have any effect in changing the z output (16)

(or)

(b) Draw the fundamental mode and pulse mode asynchronous circuit and analyze the same in detail. (16)