ISRA UNIVERSITY
FACULTY OF ENGINEERING, SCIENCE & TECHNOLOGY
Lab – 11
-1
Lab Experiment No.11
Name: _____________________________________________________ Roll No: ______________
Score:_________________ Signature:__________________________________ Date:___________
Designing of One Digit Decimal Counter
PERFORMANCE OBJECTIVE:
After the successful completion of this lab, students will be able to:
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Design, Synthesize & Simulation of One Digit Counter using Xilinx ISE Software
Simulation of One Digit Counter using ISIM Simulator.
Implementation of One Digit Counter with NEXYS2 Spartan 3E Kit using Xilinx ISE &
Adept Software.
LAB REQUIREMENTS:



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PC with Windows XP/2007 Operating System.
Xilinx ISE Design Suite 12.3 Software installed.
Digilent Adept Software.
NEXYS2 Spartan 3E Kit
DISCUSSION:
The code below implements a progressive 1-digit decimal counter
(0 9
0). A top-level diagram of the circuit is shown in figure 11.1
Figure 11.1: 1-digit decimal counter
DESIGNING PROCEDURE:
STEP1: DESIGN ENTRY
1. Invoke Xilinx ISE Design Suite 12.3 Software.
“Select File > New Project”
2. Enter the Project name mag_comp in the Name field. Verify that HDL is selected as the
Top-Level Source Type, and click on NEXT again click on NEXT and Click on Finish.
3. Now Create a New Source file; Go to Project > New Source.
Designed By: Engr. Irshad Rahim Memon
Department: Electrical Engineering
.
ISRA UNIVERSITY
FACULTY OF ENGINEERING, SCIENCE & TECHNOLOGY
Lab – 11
-2
 Select VHDL Module and Enter the source file name dcount.
 Click on Next. Enter the Input and output Ports name and click NEXT and click
Finish.
VHDL Code for the One Digit Decimal Counter is
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity counter is
Port ( clk : in STD_LOGIC;
sevenseg: out STD_LOGIC_VECTOR (6 downto 0);
anode: out STD_LOGIC_VECTOR (3 downto 0);
digit : out STD_LOGIC_VECTOR (3 downto 0));
END counter;
architecture Behavioral of counter is
signal temp_count : std_logic_vector(3 downto 0);
signal slow_clk : std_logic;
signal clk_divider : std_logic_vector(25 downto 0);
begin
frequency_divider : process (clk, clk_divider)
begin
if (clk = '1' and clk'event) then
clk_divider <= clk_divider + 1;
end if;
slow_clk <= clk_divider(25);
end process;
counting : process(slow_clk, temp_count)
begin
if slow_clk'event and slow_clk ='1' then
temp_count <= temp_count + 1;
if (temp_count= "1010") then
temp_count<="0000";
end if;
end if;
digit<= temp_count;
end process;
with temp_count select
sevenseg<="1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"1000000" when others;
anode<="1110";
end Behavioral;
Designed By: Engr. Irshad Rahim Memon
Department: Electrical Engineering
.
ISRA UNIVERSITY
FACULTY OF ENGINEERING, SCIENCE & TECHNOLOGY
Lab – 11
-3
Step 2: Simulation
After Creating project and new Source File now it is ready to simulate the Design. To simulate
the Counter follow the following steps.
1. In the Design Panel, select the Simulation radio button.
2. Select dcount Behavioral file and double click on Simulator Behavioral Model in the Process
window.
3. Select the Simulation from the menu bar and click on Restart.
4. Force the input signal (clk).
5. Select the Simulation from the menu bar and click on Run. It shows the following Simulation
result of Magnitude Comparator.
Figure: 11.2. Simulation Result for 1-digit decimal counter
Step 3: Synthesis
1. To synthesize the design, double click on the Synthesize Design option in the Processes
window.
2. Now the schematic diagram of the counter can be viewed by double clicking View RTL
Schematic under Synthesize-XST menu in the Process Window, (Figure11.3).
3. Similarly you can view the Technology Schematic Symbol by double clicking View
Technology Schematic under Synthesize-XST menu in the Process Window, (Figure 11.4).
Fig: 11.4. Schematic diagram for Counter
Fig: 11.3. Technology Schematic Symbol for
Counter
Designed By: Engr. Irshad Rahim Memon
Department: Electrical Engineering
.
ISRA UNIVERSITY
FACULTY OF ENGINEERING, SCIENCE & TECHNOLOGY
Lab – 11
-4
Step 4: Implementation
1. Before implement the design you must create the User Constraint File UCF.
2. After creating the UCF file Single Click on mag_comp.ucf file from within Project
Navigator, and then Select “Edit Constraints (Text)” from the Process window.
3. Assigning the pins to inputs and outputs of Counter and save Ucf file.
NET "clk" LOC = "B8" ;
Net "anode<0>" loc = "f17";
Net "anode<1>" loc = "h17";
Net "anode<2>" loc = "c18";
Net "anode<3>" loc = "f15";
Net "sevenseg<0>" loc = "l18";
Net "sevenseg<1>" loc = "f18";
Net "sevenseg<2>" loc = "d17";
Net "sevenseg<3>" loc = "d16";
Net "sevenseg<4>" loc = "g14";
Net "sevenseg<5>" loc = "j17";
Net "sevenseg<6>" loc = "h14";
4. After assigning the Pins double click on “Implement Design” option in the Processes
window. It will go through steps like Translate, Map and Place & Route.
5.
Now create a programming file (bit stream file) of the design. This is done by clicking
once on your top-level design in the Sources Pane, followed by a double click on
“Generate Programming File” in the process window.
6. Once the programming file (bit stream file) is generated, the file has to be downloaded to
the NEXYS2 Spartan3E device, using Digilent Adept Software.
Final Assignment :
1. Design & Simulate One Digit Decimal Counter from 0-5 and Attach simulation Result.
2. Design & Simulate One Digit Decimal Counter from 0-7 and Attach simulation Result.
Designed By: Engr. Irshad Rahim Memon
Department: Electrical Engineering
.