EEE 122/A Digital Circuit
Ch5 Synchronous Sequential
Logic
Sequential Circuits
SEQUENTIAL LOGIC
• Sequential Circuit
• Memory Elements
– Latches: S-R Latch, D Latch
– Flip-flops: D flip-flop, J-K flip-flops, T flip-flops
• Analysis of Clocked Sequential Circuit
–
–
–
–
State Equations
State Table
State Diagram
Analysis with Flip-Flops: D, JK, T
• State Reduction and Assignment
• Design Procedure
• Two types of logic circuits
– Combinational
– Sequential
• Combinational Circuit
• Sequential Circuit
– The outputs depend
The outputs depend on both
entirely on the current
present state of storage
inputs.
element and current inputs.
e.g.: Decoder, encoder,
multiplexer, demultiplexer,
Boolean function logic
inputs : :
inputs : :
Combinational
Logic
::
Combinational
Logic Circuit
outputs
Present
state
Storage
::
outputs
• Two types of sequential
circuits:
– Synchronous: is a system
whose behavior can be
determined from the
knowledge of its signal at
discrete instants of time
– Asynchronous: is a
system whose behavior
depends upon the input
signals at any instant of
time and the order in
which the inputs change
Synchronous Clocked sequential
Circuit
Inputs
Combinational
Logic
Outputs
pulses
Storage
Clock pulses
Storages are memory elements
MEMORY ELEMENTS
• Memory element: is a device which can remember
value indefinitely, or change value on command
from its inputs.
command
Memory
element
Q
stored value
Memory Elements utilize Bistable logic
devices called flip-flops.
• Memory element with clock.
Flip-Flops can change state only during a pulse transition
Two types of triggering
Pulse-triggered
Edge-triggered
Pulse-triggered
Used with latches
ON = 1,
OFF = 0
Edge-triggered
Used with Flip-flops
Positive edge-triggered
ON = from 0 to 1;
OFF = other wise
Negative edge-triggered:
ON = from 1 to 0;
OFF = other wise
command
Q
Memory
element
stored value
clock
• Clock is usually a square wave.
Positive pulses
Positive
transition
edges (0 to 1)
Negative
transition edges
(1 to 0)
Latches
• Latches is the basic types of Flip-Flops, operate with
signal levels
• They are useful for storing binary information & for
designing of asynchronous sequential circuits
SR Latch
• SR latch: is a circuit with cross-coupled NOR gates
or cross coupled NAND gates
• Two inputs: S and R.
• Two complementary outputs: Q and Q'.
SR Latch
• Active-high input S-R latch:
• Latch with NOR gates is said to be active high
10100 R
Q 11000
10001 S
Q' 0 0 1 1 0
S
1
0
0
0
1
• Block diagram:
S
Q
R
Q'
R
0
0
1
0
1
Q Q'
1 0
initial
1 0 (afer S=1, R=0)
0 1
0 1 (after S=0, R=1)
0 0
invalid!
SR Latch
• Characteristic table for active-high
input S-R latch:
S R
0
0
1
1
0
1
0
1
S
R
Q
Q'
0
0
NC
NC
1
0
1
0
1
1
1
0
0
0
1
0
No change. Latch
remained in present state.
Latch SET.
Latch RESET.
Invalid condition.
Q(t+1)
No change
Q(t)
0
Reset
1
Set
indeterminate
Q(t+1) = current state
Q(t) = last state
SR Latch
Active-low input S-R latch
active-low input S-R latches, are built of NAND gates.
R
S
Q
Q'
S
1
1
0
1
0
R
0
1
1
1
0
Q Q'
0 1
initial
0 1 (afer S=1, R=0)
1 0
1 0 (after S=0, R=1)
1 1
invalid!
when R=0 and S=1, the latch is reset (i.e. Q becomes 0)
– when R=1 and S=0, the latch is set (i.e. Q becomes 1)
– when S=R=1, it is a no-change command.
– when S=R=0, it is an invalid command.
(Sometimes, the
inputs are labelled
as S' and R'.)
SR Latch with Control input
• S-R latch + Control input (C) and 2 NAND gates a gated S-R latch.
C
0
1
1
1
1
S
x
0
0
1
1
R
x
0
1
0
1
Q Q'
No change
No change
0 1 Reset state
1 0
Set state
0 0
Indeterminate
• The control signal determine when the state of the
latch can be changed.
• C acts as an enable signal for the other input signals
Drawback: When C, S & R equal to 1; an indeterminate state occur, so when
C goes back to 0, you can not determine the next state
D Latch
• In D latch:The input R is made equal to S' gated D latch.
• D latch eliminates the undesirable condition of invalid state in the
S-R latch.
•Characteristic table:
C
0
1
1
D
X
0
1
Q
0
1
No change
Reset state
Set state
D Latch
• When C is high and ,
– D = HIGH latch is SET
– D = LOW latch is RESET
• When C is high, Q “follows” the (input data) D.
•It has ability to store data in its internal storage
•The data D is transferred to the output Q when C is enabled
•When the control C is disabled, the data that present at the
data input at the time the transition occurred is retained at
the Q output until the control is enabled again
FLIP-FLOPS
• Flip-flops are synchronous bistable devices.
• Output changes state at a specified point on a
triggering input called the clock.
• Change state either at the positive (rising) edge, or
at the negative (falling) edge of the clock signal.
Clock signal
Positive edges
Negative edges
FLIP-FLOPS
• D flip-flop, J-K flip-flop & T flip flop.
• Note the “>” symbol at the clock input.
D FLIP-FLOP
• D flip-flop: Single input D (data). On the triggering
edge of the clock pulse,
– D = HIGH Q becomes HIGH (SET state)
– D = LOW Q becomes LOW (RESET state)
• Hence, Q “follows” D at the clock edge.
Characteristic Table of D Flip-Flop
D
CLK
Q(t+1)
1
0
↑
↑
1
0
Comments
Set
Reset
↑ = clock transition LOW to HIGH
Characteristic Table of D Flip-Flop
Q(t+1)=D
Edge- Triggered D Flip-Flop
The output can change only during the transition of the
clock from 1 to 0: Negative edge of the clock
When CLK is 0; Slave is enabled Q=Y
When CLK is changed to 1; Master is enabled D
Y
When CLK return to 0; Slave is enabled Y
Q
D-Type Positive Edge Triggered Flip-Flop
• When the input clk in the positive edge triggered
Flip-flop makes positive transition, the value of D is
transferred to Q. Negative transition from 1 to 0 does not
affect the output
When clk
0, R=S=1 No change in o/p
If D=0 when clk 1, R changes to 0 (reset)
If there is change in D while clk=1, R remains at 0
When clk
0, R=1 No change in o/p
Similarly
If D=1 when clk 0
1, S changes
to 0 (set) i.e Q=1
Any change in D while clk=1, R does
affect output
D Flip-Flop with Reset or Direct input
When power is
turned ON, the state
of the Flip-Flops is
unknown
The reset is used to
force the Flip-Flop
to a particular state
independent of the
clock
J-K FLIP-FLOP
• J-K flip-flop: One of the widely used Flip-Flop
• 3 Operations can be performed with JK Filp-Flop
– J sets the Flip-Flop
– K reset the Flip-Flop
– J=k=1 complement the output Q
– J=K=0 provide no change in the output
J-K FLIP-FLOP
• J-K flip-flop circuit:
• Characteristic table:
Q
J K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+1)
0
0
1
1
1
0
1
0
Characteristic Equation:
Q(t+1) = JQ’+K’Q
J
K
Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)'
No change
Reset
Set
Toggle
T (Toggle) Flip-Flops
The output complement the input,
useful in designing binary counters
T
Q(t+1)
0
1
Q(t)
Q(t)'
Q T
Characteristics Equation Q(t+1) = T⊕ Q(t)
Characteristics Table
0
0
1
1
0
1
0
1
No change
Toggle
Q(t+1)
0
1
1
0