Lab-05-Report - The Circuits and Biology Lab at UMN

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EXPERIMENT 5--FLIP-FLOPS AND FEEDBACK DEVICES
FINAL REPORT
I. RS Latch with Enable
a). Plot the response of the gated RS NAND latch you observed for the following input
sequence in part A.1:
Q
Q'
b). Plot the response of the latch observed in part A.2 for the following input sequence:
Q
Q'
c). Does the latch always have the same output value on Q after both S and R return to 0
at the same time? If so, might this change if the upper and lower gates were swapped in the
circuit? Explain. Give two reasons why this latch should not be used with both inputs
simultaneously 1.
5.1
5.2
II. Master-Slave Flip-Flop
a). Fill in the following table based on your observations of the operation of the 7476 JK
master-slave FF in the lab. On the basis of this table, which input sets the device, which input
resets the device, and which part of the clock pulse effects changes in the state (output) of the
flip-flop.
JK
00
00
01
01
10
10
11
11
Q
Before  edge CLK
0
1
0
1
0
1
0
1
Q
While CLK = 1
Q
After _ edge CLK
b). Plot the waveforms observed for the JK master-slave flip-flop in part B.2. Do the
changes on the J and K inputs, while the clock is high, affect the output?
5.3
c). Based upon your observations in part B.3, what are the effects of the PRESET and
CLEAR lines on the 7476 FF? How are these changes affected by pulses on the J, K, and CK
lines?
III. J-K Edge-Triggered Flip-Flops
a). Using your lab results, fill in the following table for the 74LS76 negative edgetriggered FF. How does this table compare with the corresponding table for the JK master-slave
FF?
JK
00
00
01
01
10
10
11
11
Q
Before ↑ edge CLK
0
1
0
1
0
1
0
1
Q
While CLK = 1
Q
After ↓ edge CLK
b). Show the waveforms observed for the 74LS76 flip-flop in part D.2 of the experiment.
Compare this to the corresponding graph for the JK master-slave FF.
5.4
IV. Conclusion
Write a brief description of the operation of the various latches and flip-flops based on your
laboratory observations. Compare the performance of the basic latch, the master-slave flip-flop,
and the edge-triggered flip-flop. What are the advantages and disadvantages of each design?
For what applications are each best suited?
5.5
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