Combinational Logic

Changes in input values are reflected immediately
(subject to the speed of light and electrical delays)
on the outputs

Each gate has an associated “electrical delay”

Delays are often ignored for the purpose of the logic
design (but not for the real implementation!)

As soon as inputs change, the outputs change – no
memory of what happened before

(at least conceptually)
Latches & Flip-Flops
Example Needing Bit Storage

Flight attendant call button

Press call: light turns on



Stays on after button released
Press cancel: light turns off
Logic gate circuit to
implement this?
a
Call
Cancel
Q
Call
button
Cancel
Blue light
Bit
Storage
button
1. Call button pressed – light turns
on
Blue light
Call
button
Cancel
Bit
a
Storage
button
2. Call button released – light stays
on
Call
button
Cancel
Blue light
Bit
Storage
Doesn’t work. Q=1 when Call=1,
button
but doesn’t stay 1 when Call
3. Cancel button pressed – light turns
returns to 0
off
Need some form of “feedback” in the circuit
First attempt at Bit Storage

We need some sort of feedback
Does circuit on the right do what we
want?

S 0
0
t
1
0
t
1
0
Q
1
0
t
No: Once Q becomes 1 (when S=1), Q
stays 1 forever – no value of S can bring
Q back to 0

S
Q
S
0Q S 1
0
t
0Q
S 1
0
t
1Q
S 1
1
t
1Q
S 0
1
t
1Q
Basic NOR (SR) Latch




When Set = 0, Reset = 1  Q = 0
When Set = 1, Reset = 0  Q = 1
When Set = Reset = 0  Q = memory
When Set = Reset = 1  Q = 0
Reset
Set
Q
Basic NOR Latch Redrawn
S
R
Q
Q
0
0
0/1
1/0
0
1
0
1
1
0
1
0
1
1
0
0
R
S
Q
Q
memory state
Timing Analysis of Basic Latch
t1
t2
t3
t4
t5
t6
t7
t8
t9
t 10
1
R
0
1
R
Q
S
0
1
Q
0
Q
S
?
1
Q
?
0

What happens at t10??


S and R both go from 1 to 0 simultaneously
If gate delays are exactly the same  oscillation!!!
Gated SR Latch

To get better control of the state changes, we must
limit when the input signals affect the outputs
Clk
S
R
Q(t+1)
0
x
x
Q(t)
1
0
0
Q(t)
1
0
1
0
1
1
0
1
1
1
1
x
R
Q
Clk
Q
S

Outputs change only when Clk = 1

Clk acts as an Enable signal
undefined since we don't know
which stable state will result
Comments on Latches

Need to avoid the unstable state


Note that all other states have “correct” Q and Q
Can use the cross-coupled NOR approach, or can
use the cross-coupled NAND approach

All gates are the same type
S
Q
Q
Q
Clk
R
Clk
R
S
Q
Gated D Latch

Provide only a single control signal D (for Data)

D
(Data)
More common than SR latch, and simpler
S
Clk
D
Q(t+1)
0
x
Q(t)
1
0
0
1
1
1
Q
Clk
Q
R
D
Q
Clk Q
D Latch Timing Diagram

Output Q changes only when Clk = 1


Q tracks D when Clk = 1
This latch is level-sensitive since the output is
sensitive to the level of the clock
t1
t2
t3
t4
Clk
D
Q
Time
Master-Slave D Flip-Flop

Desire to remove the level-sensitive nature

Want changes in Q only on the transition of the Clk signal
from 1  0 (or from 0  1)

When Clock = 1, master D latch tracks D; slave D latch
remains unchanged (Q remains fixed)
When Clock = 0, master D latch is unchanged; slave D latch
tracks Qm

Master
D
Clock
Slave
D Q Q
D Q
Q
D Q
Clk Q
Clk Q
Q
Q
negative edge-triggered flip-flop
Timing of Master-Slave D Flip-Flop

Changes to Q occur only on the negative edge of the Clock
Clock
D
Q
Q = Q
m
s
Master
D
Clock
D
Q
Clk Q
Slave
Q
m
D
Q
Clk Q
Q
s
Q
Q
Terms, Reviewed

Latch


Gated latch



Two NANDs (or NORs) used to store one bit
Latch with an control enable, called Clk
Two basic types: SR and D, both level sensitive
Master-slave flip-flop

State changes only on clock edge; made from two gated D
latches
Registers

A flip-flop stores one bit of information

When you want to store n bits  register



n flip-flops used
Clock is shared by all so action is synchronous with clock edge
Some common register types




Simple register
Shift register
Parallel access shift register
Lots of counters: up counter, down counter, BCD counter, ring
counter, Johnson counter
Simple 4-bit Register

A standard 4 bit register using D flip flops
Parallel output
Q
D
Q
Q
Q
3
D
Q
2
Q
Q
D
Q
Q
Q
1
D
Q
Q
Parallel input
Clock
0
4-bit Register with Load Control

Controlling the load capability
Parallel output
Q
D
Q
Q
Q
3
D
Q
2
Q
Q
D
Q
Q
1
D
Q
0
Q
Q
Parallel input
Load
Clock