EEM216A
Fall 2009
Design of VLSI Circuits and Systems
Homework #1
Prof. Dejan Marković
ee216a@gmail.com
Solution
The goal of this assignment is to get familiar with the 90nm CMOS technology we use in class, and to
study technology scaling.
Problem 1: MOS Transistor Models
a) Using Spectre, generate the family of I-V curves (help: online Tutorial 1 from EE115C has detailed
instructions on how to do this) for NMOS and PMOS transistor with the following parameters:
(W/L)n = 430nm/100nm, (W/L)p = 650nm/100nm
Sweep |VDS| from 0V to 1V in 50mV increments
|VGS| = 0.4V, 0.5V, 0.7V, 1.0V
|VSB| = 0V, 0.5V
Use the 90nm model as instructed in Tutorial 1 (section NN in the transistor model). Plot all I-V
curves on one graph for NMOS and another graph for PMOS. Label bias conditions for VGS and VSB.
SOLUTION
Strategy: follow Tutorial 1 from EE115C to learn how to generate MOS I‐V curves. The results could be
exported to Excel / Matlab environment for further analysis or display. Matlab plots are show below.
Tip: you may use Excellink add‐on in Excel to interface with Matlab – see the link at classwiki…
|VSB| = 0V
|VSB| = 0.5V
300
1V
NMOS
250 W = 430n
L = 100n
PMOS I (µ A)
200
0.7V
150
100
0.5V
0.4V
50
0
0
D
D
NMOS I (µ A)
300
0.2
0.4
V
DS
0.6
0.8
PMOS
250 W = 650n
L = 100n
200
1V
150
0.7V
100
50
0
1
(V)
0
0.5V
0.4V
0.2
0.4
V
DS
0.6
0.8
1
(V)
Figure 1a. Transistor I‐V curves (absolute VDS value for PMOS shown). Device size corresponds to 1x inverter from
standard cell library. Drain current ID decreases with reverse body bias (dashed).
Universal model
b) Based on the results from the previous part, determine the following model parameters: VT0, µ, λ, γ.
(hint: you don’t need to know VDSAT) You may assume that 2ΦF = -0.6V. Which parts of the I-V
1
characteristic are the most important to be matched?
(hint: extract λ parameter from the velocity saturation curves)
Determine the parameter values for both NMOS and PMOS. In the universal analytical model,
assume that the effective channel length is Leff=70nm (in order to approximate behavior of a device
with a length of 100nm obtained by Spectre simulations).
SOLUTION
There are multiple ways to extract device parameters. A simple method follows.
ID (µA)
1b1) Extracting threshold voltage, VT0
Rationale: since VDSAT is not available, we have to extract VT0 from the saturation region.
Strategy: select two points in the saturation region from different VGS curves, (VBS = 0) and the same VDS
in both cases (e.g. VDS = 0.6V). Assume that the device is in saturation for VGS = 0.4V and VGS = 0.5V.
Exact values for the points from part 1a are obtained from Spectre simulation / Excel table.
B
VGS = 0.5V
A
VGS = 0.4V
50
0
0
0.2
0.4
0.6
0.8
1
SATURATION
VDS (V)
Figure 1b1. Two‐point method for extracting VT0 parameter. VT0 is calculated from the universal model and
saturation device.
Use the saturation model to solve for VT0:
Æ
Æ
For VSB = 0, VT = VT0. Calculated values for NMOS and PMOS are reported below:
Device
NMOS
PMOS
VT0 (VB = 0V)
165mV
−216mV
VT (VB = 0.5V)
208mV
−274mV
1b2) Extracting body‐effect parameter, γ
Using the results from VT extraction, we calculate the body‐effect parameter from the VT formula:
Æ
Calculated values are:
Device
Body‐effect
NMOS
γn = 0.16 V1/2
PMOS
γp = 0.21 V1/2
1b3) Extracting channel‐length modulation (CLM) parameter, λ
Strategy: similar to VT extraction, parameter λ is extracted by picking two points on the I‐V curves. This
time, we pick the points with equal VGS and different VDS.
2
Rationale: since we are dealing with the deep sub‐micron technology, it is important that our model
matches I‐V curves particularly well in the velocity saturation regime, so we use VGS of 0.7V or 1V.
ID (µA)
300
VGS = 1V
250
200
B
A
0
0.2
0.4
0.6
0.8
VELOCITY
SATURATION
1
VDS (V)
Figure 1b2. Two‐point method for extracting channel‐length modulation (CLM) parameter, λ. CLM is calculated
from the points in velocity saturation (this region is the most important for delay analysis of an inverter).
Use the universal current model to solve for λ:
Æ
Æ
Notice that λ greatly depends on VGS:
CLM parameter λ
|VGS| = 1V
|VGS| = 0.7V
|VGS| = 0.5V
Even smaller VGS
NMOS
λn = 0.59 V‐1
λn = 0.84 V‐1
λn = 2.04 V‐1
Increasing CLM
PMOS
λp = −0.50 V‐1
λp = −0.71 V‐1
λp = −5.17 V‐1
Increasing CLM
Discussion: we will see later on in class that the impact of λ parameter can be absorbed in delay models.
For now, note that λ largely varies with gate‐to‐source voltage. The values for large VGS are the most
important for delay analysis. Assuming that we deal with full‐swing transitions in CMOS gates and that
|VGS| corresponds to the voltage swing, CLM parameter is determined based on operating supply
voltage. Unless otherwise specified, work with the values at |VGS| = 1V (corresponding to VDD = 1V).
1b4) Extracting mobility parameter, µ
Strategy: since we don’t know VDSAT, we have to extract µ from the saturation mode (VGS = 0.4V):
From the textbook, we have, εox (SiO2) = 3.5×10−11F/m.
From Spectre model file gsclib_mos.scs, TT corner, we have toxn = 2.33 nm, toxp = 2.46nm.
Mobility parameter
|VGS| = 0.4V
NMOS
µn = 8.7×10−3 m2V/s
PMOS
µp = 4.3×10−3 m2V/s
Observation: In this technology, therefore, β = µn /µp = 2.
c) Using the parameters from (1b) and assuming VDSAT = 0.3V, generate the family of I-V curves using
the analytical model, showing information of both the original model and your own simplified model
on the same plot. Comment on any differences.
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(W/L)n = 430nm/100nm, (W/L)p = 650nm/100nm
Sweep |VDS| from 0V to 1V in 50mV increments
|VGS| = 0.5V, 0.9V
|VSB| = 0.5V
Hint: you may export results from the Spectre waveform browser by saving them into a CSV
(comma separated values) table format, load the values in your favorite software (e.g. Excel, Malab)
and plot the results from simulations and your model.
SOLUTION
Simulation results are exported to Excel / Matlab and compared with the unified model.
simulation
200
NMOS
W = 430n
L = 100n
V GS
250
9V
= 0.
PMOS I (µ A)
150
D
D
NMOS I (µ A)
250
model
100
V GS
50
0
0
= 0.5V
0.2 0.4 0.6 0.8
V
200
(V)
.9V
V SG = 0
150
100
50
0
1
PMOS
W = 650n
L = 100n
0
VSG = 0.5V
0.2 0.4 0.6 0.8
V
DS
SD
Figure 1c. I‐V curves for |VSB| = 0.5V. Simulation (solid lines) versus model (dashed lines).
1
(V)
Discussion: A better fit is observed for low VGS. This makes sense, because model parameters are extracted from
this region.
Extrapolation method (discussion)
Another method to determine the threshold voltage for the NMOS and the PMOS devices is to
extrapolate the zero-crossing of their IDS-VGS characteristic, measured for low value of VDS (e.g.
100mV). Compare these VT values with the results from (1b). Comment on any differences.
SOLUTION
We assume sufficiently low VDS that will bias the devices into linear region. From the simulation data
from (1a), we select VDS = 100mV and plot ID versus VGS. Matlab script is used to find least‐squares fit for
the data and extrapolate the ID lines: zero‐crossing with the horizontal axis is the threshold voltage, as
illustrate in Fig. 1x. Values for both zero‐body bias and 0.5V reverse bias are reported.
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100
VB=0
80
VB=0.5V
D
60
PMOS I (µ A)
NMOS I (µ A)
D
100
VT0 = 0.29 V
VT = 0.34 V
40
20
0
0
0.2 0.4 0.6 0.8
V
GS
80
60
40
VB=0.5V
VT0 = 0.32 V
VT = 0.37 V
20
0
1
VB=0
0
0.2 0.4 0.6 0.8
(V)
V
VB = 0 / VB = 0.5V
SG
1
(V)
Figure 1x. I‐V curves for |VSB| = 0.5V. Simulation (solid lines) versus model (dashed lines).
Comparison: now, let’s compare the results. So far, we have VT values estimated from the universal
model in (1b) and extrapolation‐based values from (1c). There are two other values we can look at: 1)
VT0 from the model file, and b) operating point VT from Spectre simulation. The results are summarized in
the table below.
VTH method
Body‐bias
NMOS VTH
PMOS |VTH|
Universal model (1b)
VB = 0V
VB = 0.5V
165 mV
208 mV
216mV
274 mV
Extrapolation (1d)
VB = 0V
VB = 0.5V
288 mV
339 mV
320 mV
366 mV
Model file (VT0 only)
VB = 0V
VB = 0.5V
169 mV
N/A
136 mV
N/A
Spectre OP analysis
VB = 0V
VB = 0.5V
216 mV
252 mV
277 mV
353 mV
Discussion: the extrapolation method is the closest match to Spectre OP analysis.
Subthreshold current
d) Plot the drain current and threshold voltage as a function of drain bias for the NMOS and PMOS
devices. Estimate the DIBL factor (γ).
SOLUTION
Strategy: DIBL factor is estimated from the subthreshold current formula:
Æ
Therefore, we can find γ as the slope of the log‐scale ID versus VDS plot, as show in Fig. 1e. We can use
.
two methods: 1) current formula above, 2) threshold formula with DIBL effect,
In both cases, Matlab least‐square fitting is used to find the DIBL coefficients which are indicated on the
plots in Fig. 1e and summarized below. In the current formula, n = 1.6 (typical value), T = 300K.
DIBL factor, γ
NMOS
PMOS
Current formula
0.15 V−1
0.14 V−1
VT formula
0.12 V−1
0.07 V−1
5
NMOS
PMOS
200
-3
γ = 0.15 V
-1
γ = 0.14 V
-1
p
(mV)
100
TH
10
-2
300
n
10
γ = 0.12 V
-1
n
0
NMOS
PMOS
-100
V
(log scale)
10
-1
D
I (µ A)
10
-200
-4
γ = 0.07 V
-1
p
-300
0
0.2
0.4
V
0.6
DS
0.8
-400
0
1
(V)
0.2
0.4
V
DS
0.6
0.8
1
(V)
Figure 1d. Subthreshold operation, |VGS| = 0V. I‐V curves (left), threshold voltage (right).
Short channel effects
e) Analyze the effect of channel length on threshold voltage. Simulate NMOS and PMOS devices with
W/L=10 and channel length ranging from 100nm to 500nm (in increments of 10nm). Discuss the
obtained results. Plot the absolute values of VT for NMOS and PMOS on one graph.
SOLUTION
Plot of VT as a function of channel length is shown in Fig. 1f:
PMOS
|VT| (mV)
W/L = 10
|VGS| = |VDS| = 0.5V
|VT|
NMOS
L (nm)
Figure 1e. Threshold voltage as a function of channel length.
Discussion: this shape is obtained using halo pocket‐implants in order to suppress leakage of minimum
length devices. Note that VT intersect point for NMOS and PMOS is at L = 320nm.
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Problem 2: Scaling
For this problem, assume that logic gates are ported across different technologies while keeping the W/L
ratio constant. You will need data from the low-power technology roadmap, which can be found at
http://public.itrs.net. Download the Process Integration, Devices, and Structures roadmap, edition 2005.
Simulated power dissipation of a static CMOS inverter in a 180nm CMOS technology is Pactive = 3.5µW
and Pstatic = 2nW, when the input is a 100MHz square wave with 30ps rise and fall time. Using scaling
theory and data from ITRS, predict power dissipation at the 90nm, 65nm, and 45nm nodes. Report VDD
and tox for each technology generation.
SOLUTION
Parameters are taken from the ITRS roadmap tables from years 2000 to 2005. We look at high‐
performance logic technology requirements.
Notes: ITRS 2005 edition is just a starting point for finding data for other technologies. In each edition or
update, you will see data classified in three principal categories: 1) manufacturable solution exists, and
are being optimized, 2) manufacturable solutions are known, 3) manufacturable solutions are not
known. Clearly, we want to take data with highest believability index, so we look at the first category
(“white” entries in the tables). Furthermore, we look at printed gate length (not physical gate length).
The printed gate length corresponds to actual technology node (physical length is the effective length).
Starting with 90nm technology, three tracks within ITRS exist: high‐performance, low operating voltage,
and low standby power. Scaling trends for each track are shown. Finally, the 2005 edition offers new
device structures (a nice introduction to problem 3), but provides solutions only for bulk technology.
Table on the next page summarizes key technological features for the analysis of scaling trends.
Node
180 nm [1]
Option
HP
LP
VDD (V)
1.8
1.5‐1.8
tox (nm)
1.9‐2.5
2.5
Ileak
7n
7n
(A/µm)
Ion / d,sat
750 µ
490 µ
*(A/µm) 350 µ
230 µ
Scaling analysis
Pact (W)
3.5 µ
Pleak (W)
2n
HP
1.2
2.3
90 nm [2]
LOP
LSTP
1.2
1.2
3.0
3.4
HP
1.2
2.1
65 nm [3, 4]
LOP
LSTP
1.0
1.2
2.4
3.0
HP
1.1
1.93
45 nm [5]
LOP
LSTP
0.9
1.2
2.05
2.73
10 n
100 p
1p
30 n
1n
10 p
60 n
3n
10 p
900 µ
600 µ
300 µ
980 µ
520 µ
410 µ
1020
589 µ
497 µ
2.6 µ
0.95 n
1.13 µ
9.5 p
0.57 µ
95 f
2.1 µ
2.1 n
0.58 µ
57 p
0.56 µ
0.7 p
1.36µ
2.6 n
0.42 µ
0.11 n
0.47µ
0.48p
µ
* Ion for 180nm (PMOS / NMOS current listed), Id,sat for 90nm, 65nm, and 45nm
References:
[1] 2000 Update, Table 28a
[2] 2001 Edition, Tables 35a, 36a, 36c
[3] 2003 Edition, Tables 47a, 48a, 48c
[4] 2004 Update, Tables 47a, 48a, 48c (same data as [3])
[5] 2005 Edition, Tables 40a, 41c, 41a
Analysis: scaling from 180nm to 90nm is constant field, while scaling beyond 90nm requires generalized
scaling theory. Going HP Æ LOP Æ LSTP reduces leakage mainly from tox increase.
Power is calculated by simply looking at current normalized to the device width and supply voltage.
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HP 180nm technology is a reference for HP scaling, with active current normalized to PMOS (pull‐up is
the energy consuming transition in CMOS gates). The LOP and LSTP scaling is derived from 180nm LP.
Problem 3: Power Density
Find the following references (total 8 papers) on IEEE Explore (you may link them up on classwiki).
Source: International Solid-State Circuits Conference
Year
Papers
1998
7‐6, 18‐3, 18‐6
1999
15‐5
2000
4‐2, 14‐5, 14‐8
2004
18‐5
Scan through relevant information and calculate/estimate power density (mW/mm2) normalized to 90nm
technology. Comment your findings.
SOLUTION
Case 1: Maximum Throughput Scaling
Assumptions: The chip is intended to operate faster with scaling and the power densities calculated are
in accordance with the faster operation. The chip operates at reference VDD in the new technology, unless
operated at scaled VDD to begin with. Scaling from a higher technology node to 180nm is constant‐field
scaling. General scaling is used to scale numbers from 180nm to 90nm. Refer to Lecture 2 for scaling
trends for various performance metrics. The scaled power densities are listed in the table below.
Reference
Chip 1
(7‐6)
Chip 2
(18‐3)
Chip 3
(18‐6)
Chip 4
(15‐5)
Chip 5
(4‐2)
Chip 6
(14‐5)
Chip 7
(14‐8)
Chip 8
(18‐5)
Node (nm)
500
90
250
90
280
90
250
90
250
90
250
90
350
90
130
90
VDD (V)
3.3
0.79
1.5
0.72
2
0.86
2.5
1.2
3.3
1.58
1.05
0.504
3.3
1.13
1.25
1.15
P(W)
6
0.347
0.11
0.025
3
0.55
2.3
0.533
4
0.933
0.00066
1.53x10‐4
5
0.59
0.25
0.21
8
A (mm2)
167
5.41
84.6
11.1
60
6.24
273.7
35.9
207
27.175
20
2.625
169
11.25
‐
‐
PD (mW/mm2)
35.9
64.68
1.3
2.3
50
88.88
8.4
14.93
19.32
34.35
0.033
0.058
29.6
52.62
‐
‐
Case 2: Constant Throughput Scaling
Assumptions: The chip is intended to work with the same throughput even after scaling to 90nm. This
allows for scaling the supply voltage in the new technology. Power densities are calculated at the supply
voltage that achieves the same throughput as the original chip. Scaling from a higher technology node to
180nm is constant‐field scaling. General scaling is used to scale numbers from 180nm to 90nm. Refer to
Lecture 2 for scaling trends for various performance metrics. The values of VDD that match the throughput
are obtained from a Spectre simulation for tp vs. VDD for a fan‐out‐4 inverter chain.
Reference
Chip 1
(7‐6)
Chip 2
(18‐3)
Chip 3
(18‐6)
Chip 4
(15‐5)
Chip 5
(4‐2)
Chip 6
(14‐5)
Chip 7
(14‐8)
Chip 8
(18‐5)
Node (nm)
500
90
250
90
280
90
250
90
250
90
250
90
350
90
130
90
VDD (V)
3.3
0.41
1.5
0.48
2
0.52
2.5
0.7
3.3
0.87
1.05
0.38
3.3
0.58
1.25
0.94
P(W)
6
0.093
0.11
0.011
3
0.201
2.3
0.181
4
0.283
0.00066
8.69x10‐5
5
0.155
0.25
0.14
A (mm2)
167
5.41
84.6
11.1
60
6.24
273.7
35.9
207
27.175
20
2.625
169
11.25
‐
‐
PD (mW/mm2)
35.9
17.19
1.3
0.99
50
32.31
8.4
5.05
19.32
10.413
0.033
0.033
29.6
13.77
‐
‐
Discussion: Scaling to lower technology nodes offers a faster operation but increases the power density.
If the throughput is kept constant, while scaling supply voltage, scaling can reduce the power density.
9