A Reconfigurable FIR Filter Architecture to Trade Off
Filter Performance for Dynamic Power Consumption
N. Sriram & J. Selvakumar
Department of Electronics and Communication Engineering,
SRM University, Kattankulathur,Tamilnadu – 603203, India.
1
E-mail: sriram10688@gmail.com, selva2802@gmail.com
Abstract – In order to achieve the goals of business, various
channel of communications to customers have to be
developed through technology. In the present day banking,
total automation of banking operation and is an
imperative for all banks to attract more customers,
provide efficient service and survive the competition
,apart from achieving the profit ,which is the main goals of
the business . Mobile banking is one of the alternatives
channels available to customer for quick and efficient
service at anytime and anywhere. Banks can also use
unable banking for increasing the efficiency of their staff
create a platform for better customer service and improve
relationship with their customers.
Where N represents the length of FIR filter, 𝐶𝑘
the kth coefficient, and x( n - k) the input data at time
instant n - k. In many applications, in order to achieve
high number of taps are necessary.
Many previous efforts for reducing power
consumption of FIR filter generally focus on the
optimization of the filter coefficients while maintaining
a fixed filter order[3]–[5]. In those approaches, FIR
filter structures are simplified to add and shift
operations, and minimizing the number of
additions/subtractions is one of the main aims of the
research. But, one of the drawbacks in those approaches
is once if filter architecture is decided, the coefficients
cannot be changed; therefore, those techniques are not
suitable to the FIR filter with programmable
coefficients. Approximate [8] signal processing
techniques are also used for the design of low power
digital filters [9], [10].In [11] filter order dynamically
varies according to the energy band of the input signal.
However, the approach suffers from slow filter-order
adaptation time due to energy computations in the
feedback mechanism. Previous studies in [9] show that
the data samples or filter coefficients before the
convolution operation has a desirable energy-quality
characteristic of FIR filter. However, the overhead
associated with the real-time sorting of incoming
samples is too large. Reconfigurable FIR filter
architectures are previously proposed or low power
implementations [9]–[11] or to realize various frequency
responses using a single filter [12]. For low power
architectures, variable input word-length and filter taps
[9], different coefficient word-lengths [8], and dynamic
reduced signal representation [11] techniques are used.
In those works, large overhead is incurred to support
reconfigurable schemes such as arbitrary nonzero digit
assignment or [11] programmable shift [10].
Keywords: Mobile Banking, SMS Services, Application of
Mobile Phone.
I.
INTRODUCTION
The vast developing technological areas like
mobile, computing and portable multimedia generally
communication applications has increased the demand
for low power systems. The digital signal processing
(DSP) is one of the technologies most contributed in
processing huge amount of data with higher operational
speed in communication systems. Many application
systems based on DSP, especially the recent nextgeneration communication systems, require extremely
fast processing of large amount of digital data. Most of
DSP applications such as finite impulse response (FIR)
filtering and fast Fourier transform (FFT) require
additions and multiplications.
One of the most widely used operations performed
in DSP is finite impulse response (FIR) filtering. The
input-output relationship of the linear time invariant
(LTI) FIR filter can be expressed as the following
equation:
y (n) =
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In this paper, we propose a simple yet efficient low
power reconfigurable FIR filter architecture, where the
filter order can be dynamically changed depending on
the amplitude of both the filter coefficients and the
inputs. When the data sample multiplied to the
coefficient is so small as to process the effect of partial
sum in FIR filter, the multiplication operation can be
simply canceled. Since the multipliers have a significant
impact on the performance of the entire system, many
high-performance algorithms and architectures have
been proposed to accelerate multiplication[1-10].
Various multiplication algorithms such as Booth [11],
modified Booth, Braun, Baugh-Wooley have been
proposed. The modified Booth algorithm reduces the
number of partial products to be generated and is known
as the fastest multiplication algorithm. Many researches
on the multiplier architectures including array, parallel
and pipelined multipliers have been pursued and the
pipelining is the most widely used technique to reduce
the propagation delays of digital circuits. This paper
proposes the high-speed multiplier with very deep
pipelines based on the modified Booth algorithm. We
determined the number of pipeline stages and the
positions for the pipeline registers to be inserted by
exhaustive experiments. The resultant multipliers show
a good performance enough to be used in the very highspeed applications. The filter performance degradation
can be minimized by controlling the error bound as
small as the quantization error or signal to noise power
ratio (SNR) of given system.
particular tap and the multiplier generates the product of
the two register contents. The latter product serves as
the output of the cell, and the weighted sum that
constitutes the FIR filter output is generated by adding
the outputs of all of the cells. FIR filters are said to be
finite because they do not have any feedback. FIR
digital filters are widely used in DSP by the virtue of its
stability, linear phase, fewer finite precision error and
efficient implementation.
Fig.1. Direct Form FIR filter
2. Conventional Method:
1. Reconfigurable Fir Filtering To Trade Off Filter
Performance And Computation Energy:
FIR filtering operation performs the weighted
summations of input sequences, called as convolution
sum, which are frequently used to implement the
frequency selective—low-pass, high-pass, or bandpass—filters. Generally, since the amount of
computation and the corresponding power consumption
of FIR filter are directly proportional to the filter order,
if we can dynamically change the filter order by turning
off some of multipliers, significant power savings can be
achieved. However, performance degradation should be
carefully considered when we change the filter order.
The coefficients of a typical 25-tap low-pass FIR filter.
The central coefficient has the largest value—the
coefficient 𝐶𝑘 has the largest value in the 25-tap FIR
filter—and the amplitude of the coefficients generally
decreases as k becomes more distant from the center tap.
The primary goal of this work is to reduce the
dynamic power of the FIR filter.
1) A new reconfigurable FIR filter architecture with
real-time input and coefficient monitoring circuits is
presented. Since the basic filter structure is not
changed, it is applicable to the FIR filter with
programmable coefficients or adaptive filters.
2) We provide mathematical analysis of the power
saving and filter performance degradation on the
proposed approach. The analysis is verified using
experimental results, and it can be used as a
guideline to design low power reconfigurable
filters.
The data inputs x(n) of the filter, which are
multiplied with the coefficients, also have large
variations in amplitude. Therefore, the basic idea is that
if the amplitudes of both the data input and filter
coefficient are small, the multiplication of those two
numbers is proportionately small; thus, turning off the
multiplier has negligible effect on the filter
performance. For example, since two’s complement data
format is widely used in the DSP applications, if one or
both of the multiplier input has negative value,
multiplication of two small values gives rise to large
switching activities, which is due to the series of 1’s in
the MSB part. By canceling the multiplication of two
small numbers, considerable power savings can be
achieved with negligible filter performance degradation.
II. EXISTING FIR ARCHITECTURES
1.
General FIR Filter:
In this existing type, a direct FIR filters consist of
cells equal in number to the length of the filter i.e. the
number of data taps. Each cell consists of a storage
register, a second register and a multiplier. The storage
register stores the data tap values, which are digital
samples of the signal being processed by the filter. The
second register stores the filter coefficients for a
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adaptively due to designer’s considerations, AD can be
implemented using a simple comparator.
In the fixed point arithmetic of FIR filter, full operand
bit widths of the multiplier outputs is not generally used.
In other words, as shown in Fig. 1, when the bit-widths
of data inputs and coefficients are 16, the multiplier
generates 32-bit outputs. However, considering the
circuit area of the following adders, the LSBs of
multipliers outputs are usually truncated or rounded off,
(e.g., 24 bits are used in Fig. 1) which incurs
quantization errors. When we turn off the multiplier in
the FIR filter, if we can carefully select the input and
coefficient amplitudes such that the multiplication of
those two numbers is as small as the quantization error,
filter performance degradation can be made negligible.
Dynamic power consumption of CMOS logic gates
is a strong function of the switching activities on the
internal node capacitances. In the proposed
reconfigurable filter, if we turn off the multiplier by
considering each of the input amplitude only, then, if the
amplitude of input abruptly changes for every cycle, the
multiplier will be turned on and off continuously, which
incurs considerable switching activities. Multiplier
control signal decision window (MCSD) in Fig. 2 is
used to solve the switching problem. Using ctrl signal
generator inside MCSD, the number of input samples
consecutively smaller than 𝑥𝑡ℎ are counted and the
multipliers are turned off only when consecutive input
samples are smaller than 𝑥𝑡ℎ . Here, m means the size of
MCSD [in Fig. 2, m is equal to 4]. Fig. 2 shows the ctrl
signal generator design.
In the following, we denote threshold of input and
threshold of coefficient as 𝑥th and 𝐶𝑡ℎ , respectively. By
threshold, we mean that when the filter input x(n) and
coefficient 𝐶𝑘 are smaller than 𝑥𝑡ℎ and 𝐶𝑡ℎ ,
respectively, the multiplication is canceled in the
filtering operation. When we determine 𝑥th and, 𝐶th the
trade-off between filter performance and power savings
should be carefully considered.
Fig 3 Proposed reconfigurable FIR filter architecture
As an input smaller than 𝑥𝑡ℎ comes in and AD
output is set to “1”, the counter is counting up. When the
counter reaches, the ctrl signal in the figure changes
to“1”, which indicates that consecutive small inputs are
monitored and the multipliers are ready to turn off. One
additional bit, 𝑖𝑛𝑐𝑡_𝑛 in Fig. 2, is added and it is
controlled by ctrl. The 𝑖𝑛𝑐𝑡_𝑛 accompanies with input
data all the way in the following flip-flops to indicate
that the input
sample is smaller than and the
multiplication can be canceled when the coefficient of
the corresponding multiplier is also smaller than 𝐶𝑡ℎ .
Once 𝑖𝑛𝑐𝑡_𝑛 the signal is set inside MCSD, the signal
does not change outside MCSD and holds the amplitude
information of the input. A delay component is added in
front of the first tap for the synchronization between
x(n) and in 𝑖𝑛𝑐𝑡_𝑛 Fig.2 since one clock latency is
needed due to the counter in MCSD. In case of adaptive
filters, additional ADs for monitoring the coefficient
amplitudes are required as shown in Fig. 2. However, in
the FIR filter with fixed or programmable coefficients,
Fig 2 Amplitude Detector
2. Architecture Of Reconfigurable Fir Filter:
A structure to in this section, we present a direct
form (DF) architecture of the reconfigurable FIR filter,
which is shown in Fig.2. In order to monitor the
amplitudes of input samples and cancel the right
multiplication operations, amplitude detector (AD) in
Fig.3 is used. When the absolute value of x(n) is smaller
than the threshold 𝐶𝑡ℎ , the output of AD is set to “1”.
The design of AD is dependent on the input threshold
𝑥th , where the fan in’s of AND and OR gate are
decided by 𝑥th . If 𝑥𝑡ℎ and 𝐶𝑡ℎ have to be changed
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since we know the amplitude of coefficients ahead, extra
AD modules for coefficient monitoring are not needed.
well. The trade-off between the power saving ratio and
the MSE for different m values in case of a tap equiripple filter with 𝑥𝑡ℎ and 𝐶𝑡ℎ .
When the amplitudes of input and coefficient are
smaller than𝑥𝑡ℎ and 𝐶𝑡ℎ , respectively, the multiplier is
turned off by setting signal ∅𝑛 [Fig. 2] to“1”. Based on
the simple circuit technique A low complexity
reconfigurable DCT architecture to trade off image
quality for power consumption in the multiplier can be
easily turned off and the output is forced to “0”. As
shown in the figure, when the control signal ∅𝑛 is “1”,
since PMOS turns off and NMOS turns on, the gate
output is forced to “0” regardless of input. When ∅𝑛 is
“0”, the gate operates like standard gate. Only the first
gate of the multiplier is modified and once ∅𝑛 the is set
to “1”, there is no switching activity in the following
nodes and multiplier output is set to “0”.
Fig 4 Schematic of ctrl signal generator. Internal counter
sets ctrl signal to “1” when all input samples inside
MCSD are smaller than xth (m=4case).
The area overheads of the proposed reconfigurable
filter are flip-flops for 𝑖𝑛𝑐𝑡_𝑛 signals, AD and ctrl signal
generator inside MCSD and the modified gates for
turning off multipliers. Those overheads can be
implemented using simple logic gates, and a single AD
is needed for input x(n) monitoring as specified in Fig.
2. Consequently, the overall circuit overhead for
implementing reconfigurable filter is as small as a single
multiplier.
2.
Following are the specifications on the FIR filters
implemented.
1.
Input sequence and coefficients are 16-bit data with
fractional part of 15 bit. Hence, the data range is [1,1].
2.
The outputs of the multiplier in the FIR filter are
quantized into 16 bit and the final filter output is
24 bit.
3.
We use as an input threshold 𝑥𝑡ℎ , and coefficient
threshold, 𝐶𝑡ℎ . The values of MCSD window
length, m, are differently assigned for the filters.
The values of 𝑥𝑡ℎ , 𝐶𝑡ℎ , and can be controlled by
users considering the performance degradation and
power savings trade-off presented
III. DESIGN CONSIDERATIONS OF THE
RECONFIGURABLE FIR FILTER
1.
Reconfigurable Fir Filter Specifications:
Design Considerations
In following discussions, as a metric of power
savings, we use the power consumption ratio, , which
means the ratio of the reconfigurable filter power
consumption to the conventional filter power . As a
measure of filter performance degradation, we use
mean-square error (MSE) between the proposed
reconfigurable filter output and original filter output.
The most important factors that have a large effect on
the proposed filter performance and power consumption
are 𝑥𝑡ℎ and 𝐶th . When 𝑥𝑡ℎ and 𝐶𝑡ℎ are set too large, it
can give rise to large power savings with considerable
distortion in the filter output. On the other hand, if 𝑥𝑡ℎ
and 𝐶th are too small, power savings become trivial. The
other one to be considered is , the length of MCSD. The
number of input samples whose m ( x axis) consecutive
input values are smaller than input threshold. The input
signals used in the simulation are more than ten samples
of sounds and speeches. If we choose a specific m value
in the axis, the total number of canceled multiplications
is the accumulated number of samples from the selected
value to the right. Therefore, m if becomes larger, the
number of input samples that make multipliers turned
off decreases; then, power reduction becomes smaller
and filter performance degradation becomes lower as
III. PROPOSED SYSTEM
1.
Proposed Pipeline Modified Booth Multiplier
Architecture:
The
proposed
architecture
improves
the
performance and power saving of FIR filter. In the
proposed architecture the multiplier in conventional is
replaced with pipelined modified booth multiplier. This
pipelined architecture efficiently saves power and
improves performance with efficient trade off
comparatively with conventional architecture. The
pipeline technique is widely used to improve the
performance of digital circuits. As the number of
pipeline stages is increased, the path delays of each
stage are decreased and the overall performance of the
circuit is improved. We investigated various pipeline
schemes to find the optimum number of pipeline stages
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and the positions for the pipeline registers to be inserted
in order to obtain the high-speed modified Booth
multiplier.
1.
modified Booth multiplier, the Wallace tree is
partitioned into seven pipeline stages.
3.
Basic 3-stage Pipelined Multiplier:
Pipelines in Full Adders:
The delays of the basic 3-stage pipelined multiplier
are reduced by half compared to the nonpipelined
multiplier. By applying 3-stage pipelines in the Wallace
tree, the delay of the critical path is reduced again by
half. In this case, the critical path becomes the full
adders in the Wallace tree. We inserted the pipeline
registers in the full adders too. Fig. 6 shows the
architecture of the 2-stage pipelined full adder. By using
this adder in the Wallace tree, the overall performance is
improved more.
At first, we partitioned the modified Booth
multiplier into three pipeline stages according to the
functionality of the circuit as shown in Fig. 4. The delay
of the critical path of the 3-stage pipelined multiplier is
reduced approximately by half compared to the
nonpipelined one. The critical path of the 3-stage
pipelined multiplier is in the Wallace tree because it
requires the most intensive computation. It means that
we can reduce the delays further by adding more
pipeline registers within the Wallace tree.
Fig. 5 Wallace tree with 3-stage pipelines
3.
The delays of the basic 3-stage pipelined multiplier
are reduced by half compared to the nonpipelined
multiplier. By applying 3-stage pipelines in the Wallace
tree, the delay of the critical path is reduced again by
half. In this case, the critical path becomes the full
adders in the Wallace tree. We inserted the pipeline
registers in the full adders too. Fig. 6 shows the
architecture of the 2-stage pipelined full adder. By using
this adder in the Wallace tree, the overall performance is
improved more.
Fig. 5 Modified Booth multiplier with 3-stage pipelines
2.
Pipelines in Full Adders:
Pipelines in Wallace Tree:
The number of partial products of the N-bit
modified Booth multiplier is N/2. In case of the 8-bit
modified Booth multiplier, the number of partial
products is four. Instead of using an additional circuit
for the 2’s complement operations, we used the signals
‘Neg0’ ~ ‘Neg3’ as shown in Fig. 2. Therefore, the
number of rows is five because of four partial products
and ‘Neg3’. The Wallace tree adds three rows and
generates two rows. One row represents the carries and
the other row represents the sums. The Wallace tree
shows a good performance by using the carry save
adders instead of the ripple carry adders. It is, however,
still the most critical part of the multiplier because it is
responsible for the largest amount of computation.
Naturally the pipeline registers should be inserted within
the Wallace tree to improve the performance.
Considering that the Wallace tree computes the partial
products in three steps for the 8-bit modified Booth
multiplier, we partitioned the Wallace tree into three
pipeline stages as shown in Fig. 5. In case of the 16-bit
Fig. 6 Pipelines in Full Adders
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IV. EXPERIMENTAL RESULTS:
TABLE 2
Synthesis on the power savings and performance
degradation of the proposed reconfigurable FIR filter are
presented in this subsection. Power consumption is
measured in the spice level simulations. Architectures
are compared in parameters like area, power and delay.
The comparison table states the architecture which has
low power, less area and minimum delay. The Xilinx
12.3i ISE used for synthesizing purposes. Table shows
the synthesis results of Conventional and Proposed
Architectures 16-tap FIR filter that has a coefficient
word length of 16 bits.
The Performance Comparison Of The Synthesis Results
Between The Existing, Proposed And Direct Form
Methods Methods.
Speed
(nS)
Architectures
Filter
order
Direct
form(DF)
Conventional
Proposed
(CA)
(PA)
4tap
8.3
4.3
3.1
8tap
7.6
3.45
2.7
TABLE 1
The Power Comparison Of The Synthesis Results
Between The Existing And Proposed Method
Graph 2 Performance Comparison
power
(mW)
Filter
order
10
Architectures
8
Direct
form(DF)
Conventional
Proposed
(CA)
(PA)
4tap
400
334
314
8tap
700
330
297
6
4tap
4
8tap
2
0
DF
CA
PA
Graph 1 Power Comparison
800
700
600
500
400
300
200
100
0
Performance comparison between the existing and
proposed method is represented in table 2. The Proposed
architecture is operating at a higher speed improving
filter performance or reduced delay compared to all
other architectures. The Direct form consumes more
time and the proposed method gets less delayed
compared to the existing one for the operational output,
thus reducing the delay. This architecture holds good for
higher order filters and filter applications which uses
dynamically changing filter orders.
4tap
8tap
DF CA PA
V. CONCLUSION
In this paper, we propose pipelined modified booth
multiplier architecture in conventional architecture to
design a efficient lowpower reconfigurable FIR filter.
This architecture is to allow efficient trade-off between
the filter area, filter performance and computation
energy. In the proposed reconfigurable filter, the input
data are monitored and the multipliers in the filter are
turned off when both the coefficients and inputs are
small enough to reduce the effect on the filter output.
Therefore, the proposed pipelined modified booth
multiplier reconfigurable filter architecture dynamically
Power comparison between the existing and
proposed method is represented in table 1. The Proposed
architecture is offering a good power compare to all
other architectures. The Direct form consumes more
power and the proposed method consumes less power
compare to the existing one, thus improving in power
savings. This architecture holds good for higher order
filters and filter applications which uses dynamically
changing filter orders.
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changes the filter order to achieve significant power
savings with improvements in performance and power
consumption compared to conventional architecture.
According to the analysis, power savings and filter
performance are represented as strong functions of
MCSD window size, the input and coefficient
thresholds, and input signal characteristics. The
proposed approach can be applicable to other areas of
signal processing, where power savings, performance
and filter area should be carefully considered. The
architecture we propose in this paper can assist in the
design of FIR filters and its implementation for high
speed or reduced delay and lowpower applications.
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