Faculty of Information Engineering & Technology
Electrical & Electronics Department
Course: Microelectronics Lab ELCT605
Spring 2015
Eng. Salma Hesham
Dr. M. Abd El Ghany
DIGITAL LAB REPORT 3
MODELING OF COMBINATONAL
CIRCUITS USING VHDL
Name
ID
Grade:
Lab Group
/10
1
Modeling of Combinational Circuits
Using VHDL
 Lab Task: 1-Digit BCD-Adder (Individual Submission)
 Lab Assignment:1- Digit BCD Adder-Subtract (Individual
Submission)
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 Lab Task: One-Digit BCD Adder
Fig. 1 One-Digit BCD Adder
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1. Four-bit Adder:
Fig. 2 Four-bit Adder
A. Full Adder:
Create a new source of type VHDL module named “FA”. Write the VHDL code
of a full adder using dataflow modeling.
Inputs:
A, B, Ci
Outputs:
S, Co
Full Adder VHDL code
B. Four-bit Adder:
Create a new source of type VHDL module named “Adder4bit”. Write the
structural VHDL code of the 4-bit adder using the FA component in part (1. A).
4-bit inputs: A, B
5-bit output: S
4-bit Adder structural VHDL code
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C. Create a new source of type VHDL Testbench to test the 4-bit adder in part (1.B).
Use the following test cases: 1+6, 9+6 and 9+8
Stimulus Process from the VHDL TestBench code
D. Perform a behavioral simulation to check the output according to the provided
test cases.
Simulation Output
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2. Five-bit adder
Fig. 3 Adder 5-bit
A. Create a new source of type VHDL module named “Adder_5bit”. Write the
structural VHDL code of the 5-bit adder using the FA component in part (1.
A) using concurrent for-generate statement instead of explicitly creatings 5
instances of the full adder.
5-bit Adder VHDL code using for-generate
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3. Four-bit “ > 𝟗 ” Detector Circuit:
Fig. 4 Four-bit > 9 Detector
A. For a 4-bit number 𝑋 = 𝑥3 𝑥2 𝑥1 𝑥0 , derive the conditions where this number
would be greater than 9. Write down the simplest equation for the output 𝐺.
𝐺=
B. The following two VHDL codes model the 4-bit “> 9” detector circuit. Specify
whether each code is correct or not in terms of logical and synthesis problems.
VHDL Code 1:
entity greater_9_detector is
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC);
end greater_9_detector;
architecture Behavioral of greater_9_detector
is
begin
Process(x)
begin
if(x(3)='1')then
G<=x(2) or x(1);
end if;
end process;
end Behavioral;
Resulting RTL Schematic
Poblem:
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VHDL Code 2:
entity greater_9_detector is
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC);
end greater_9_detector;
architecture Behavioral of greater_9_detector
is
begin
Process(x)
begin
if(x(3)='1')then
if(x(2)='1' or x(1)='1')then
G<='1';
end if;
end if;
end process;
end Behavioral;
Resulting RTL Schematic
Problem:
C. Creat a new source of type VHDL module named “detector_circuit”. Model the
circuit shown in Fig. 3 using complete and correct conditioning.
Use the concurrent conditioning statement “when-else” or “with-select”
instead of the sequential if-statements.
Detector Circuit VHDL code
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Resulting RTL Schematic
4. Two-to-1 5-bit Multiplexer
Fig. 5 5-bit 2-to-1 Mux
A. Create a new source of type VHDL module named “Mux2x1_5bit”. Model the
5-bit multiplexer using concurrent when-else or with-select statement.
5-bit Multiplexer VHDL code
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5. One-Digit BCD Adder Top Module:
A. Create a new source of type VHDL module named “BCD_Adder”. Use the
components created in parts (1-4) to write the structural code of the BCD
adder shown in Fig. 1.
One-Digit BCD Adder VHDL code
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B. Create a new source of type VHDL Testbench to test the BCD adder in part
(5.A). Use the following test cases: 1+6, 9+6 and 9+8
Stimulus Process from the VHDL TestBench code
C. Perform a behavioral simulation to check the output according to the provided
test cases.
Simulation Output
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 Lab Assignment: One-Digit BCD Adder/Subtractor
1. Show how to modify the block diagram in Fig. 1 to get the one-digit BCD
Adder/Subtractor. Draw the new block diagram.
Block Diagram of one-digit Adder/Subtractor
2. Write the VHDL code only of the modified part.
VHDL code of the modified block
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3. Write the VHDL code of the top module after modification
One-Digit BCD Adder/Subtractor VHDL code
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4. Create a new source of type VHDL Testbench to test the BCD adder in part (3).
Use the following test cases: 1+6, 9+6 and 9+8
Stimulus Process from the VHDL TestBench code
5. Perform a behavioral simulation to check the output according to the provided test
cases. Comment whether the output corresponds to the implemented logic or
not.
Simulation Output
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