adder_cavallar

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Application of Addition Algorithms
Joe Cavallaro
Overview
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Addition algorithms – core operation
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Fixed-point core algorithms easy to implement
Basic adder design from full adder cell
Ripple carry addition – O(n)
Carry propagation bottleneck
“Fast” algorithms control carry transport
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Wireless Communications Applications
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Key to all matrix algorithms.
GPP and DSP processors use a given algorithm
Flexible choice in ASIC and FPGA designs
Multiuser Detection – Addition bottleneck since
multiplications can be eliminated via hard decisions
Area-time complexity in choice of Adders
Redundant Arithmetic and On-Line
Addition
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Traditional number systems have “0” and “1” and
work from LSB to MSB.
Redundant arithmetic allows “-1”, “0” and “1” bits per
digit – implies multiple representations and “error
correction”
On-Line arithmetic is bit serial from MSB to LSB
Allows for efficient pipelines and allows quick sign
detection
Challenge is to quantify speedup
Adder Equations
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Full Adder Cell
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S_I = x_I XOR y_I XOR c_I
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C_I+1 = x_I AND y_I OR c_I AND (x_I OR y_I)
Ripple Carry Adder
Carry look-ahead Adder
(f,r) Gate Tree
Tree Structure Adder – T > log 2n
Manchester Carry Chain
Carry Skip Adder – comparable to CLA
Counter Cell – Multi-operand ->
Multiplication
Carry-Save Adders
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Basic cell generate c and s output
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S = (x + y + z) mod 2
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C = ((x + y + z) – s) / 2
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Final carry-propagate adder at bottom of tree
Carry Save Adder – 4 Operands
Carry Save Adder Tree for 6 Operands
Levels in the CSA Tree
Pipelined Design
Timing Diagram for Pipeline
Summary
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Overview of addition algorithms
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Block structures for RCA, CLA, CSA
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Introduction to Redundant arithmetic and On-line
arithmetic
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Application to ASICs for Multiuser Detection
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Reference: Israel Koren
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