LU DECOMPOSITION
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LU DECOMPOSITION
LU DECOMPOSITION
Project Deliverables:
Given the computation flow of LU Decomposition of a 4X4 square matrix and the
corresponding dataflow diagram, architect a pipelined VHDL implementation
such that a single pipeline stage contains a single processing element
1. Assume 4 bit wide data throughout.
2. Also assume that the testbench code includes the read/write memory.
1. aij from the memory is sent to PEij as an input.
2. uij and lij values are sent back to memory as outputs of the corresponding
PEs.
3. Explicit instantiations of memory elements are not required – supply aij
values from testbench, and read lij and uij values into the testbench.
3. Describe your pipelined design implementation in your report.
4. Give printouts of the VHDL codes, including testbench in the report.
5. Attach the waveform printouts in the report.