EE 5323 Project
16 Bit Sklansky Adder
Phase 1 Report
Yuan Xu
4139225
xuxxx488@umn.edu
Contents
•
•
•
•
•
•
Literature review
Schematic
Netlist
Design Optimization
Waveforms of test cases
Power consumption at the maximum
operating frequency
Literature Review
• Sklansky adder belongs to tree adder family.
• The difference between Sklansky adder and
other tree adders is prefix network.
• Compare to other tree adders, Sklansky adder
has minimum logic levels, wiring tracks, but
maxinum fanout. Also, it has largest delay at
the same condition.
Literature review
Structure of 16 bit Sklansky Adder
(Black square is dot operator
Grey square is empty dot operator
White triangle is buffer)
15 14 13 12 11 10
15:14
13:12
11:10
15:12 14:12
15:8
14:8
11:8 10:8
13:8
9
9:8
8
7
6
7:6
7:4
5
5:4
6:4
4
3
2
3:2
3:0
1
0
1:0
2:0
12:8
15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Reference List
• D.Harris, “ A Taxonomy of Parallel Prefix Networks,
Signals ”, Systems and Computers, 2003.
Conference Record of the Thirty-Seventh
Asilomar Conference on, 2, 2213-2217 Vol.2,2003
• J. Sklansky, “Conditional-sum addition logic,” IRE
Trans. Electronic Computers, vol. EC-9, pp. 226231, June 1960.
• J M. Rabaey, A. Chandrakasan, B. Nikolic, “ Digital
Integrated Circuits-A Design Perspective (Second
Edition)”, Prentice Hall, 2003
Schematic of adder
• Precomputation (Generating Propagate value
P and Generate value G).
• Gi:i=Ai·Bi
• Pi:i=Ai⊕Bi
Schematic of adder
• Bubble shifted Dot operator
Schematic of adder
• Empty empty dot operator
Schematic of adder
• Bubble shifted empty dot operator
Schematic of adder
• Overall view of adder
HSPICE netlist see attached file
•
•
•
•
Sizing:
NMOS: L=50nm, W=90nm
PMOS: L=50nm, W=135nm
Temperature: 25°C
Design Optimization
• Sizing the gate to minimum size (90nm) can
reduce area and power
• By using bubble shifting, we save totally 28
inverters, and 4 inverters on the critical path
• Adding the buffer can effectively reduce delay.
Setting stage=1, fanout=4
Waveforms of test cases
• Worst case: For Sklansky adder, the worst case
happens when inputs are 7FFF+0001. Since G
will propagate from A_0 to S_15 which is the
critical path.
Waveforms of test cases
• Worst case 7FFF+0001
• A_0-A_15
B_0-B_15
Cout,S_0-S_15,
•
•
•
Waveforms of test cases
Other cases( FFFF+0001, 7FFF+0001, 3FFF+0001, 1FFF+0001, 0FFF+0001, 07FF+0001,
03FF+0001
A_0-A_15
B_0-B_15
Cout,S_0-S_15
Power consumption at the maxinum
operating frequency, V=1.1V
• Worst case Delay= 4.11E-10 S
• Ptotal=4.50E-05W
• Pmax=1.64E-03W