CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
SMUJAN15
ASSESSMENT_CODE BCA1040_SMUJAN15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
5710
QUESTION_TEXT
Explain the important characteristics of DAC devices.
Characteristics of DAC devices.
Resolution (2 marks)
Maximum sampling frequency (2 marks)
SCHEME OF EVALUATION
Monotonicity (2 marks)
THP + N (2 marks)
Dynamic range(2 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
5711
QUESTION_TEXT
Explain the practical operation & applications of digital to
analog converters.
SCHEME OF
EVALUATION
Practical operation:
Instead of impulses…….. sampling intervals
These numbers are……….reconstructed signal (2 marks)
Piecewise constant signal……..reconstruction filter(2 marks)
However this filter means …..sampled data. (2 marks)
Applications
Audio(2 marks)
Video(2 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
5712
QUESTION_TEXT
What are shift registers? Explain SISO shift registers.
SCHEME OF
EVALUATION
Shift registers is a group …… activated (1 mark)
SISO(serial-in-serial-out)
Destructive readout:
These are……and lost (1 mark)
The data are stored…..4-Bit register (1 mark)
To give idea of…..output pin and so on(2 mark)
So the serial output of entire….right most bit (2 mark)
Non-destructive readout:
Non destructive readout can be……end of the register(2
mark)
However, when the R/W ….lost from the system(1 mark)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72381
QUESTION_TEXT
Explain the rules for simplifying functions using K–map.
SCHEME OF
EVALUATION
Summary of rules for simplifying functions using Karnaugh maps
1. While implementing minterm function, cells in K-map should be
included with all 1’s but not 0’s. While implementing maxterm
function, cells in K-map should be included with all 0’s but not 1’s.
2. Group only cells which are horizontally or vertically adjacent to
each other.
3. In –map the group size should be in power of 2 .i.e., group size
can be 1, 2, 4, 8 and so on.
4. The largest size groups are used to obtain the simplest form. Use
the fewest groups possible.
5. In order to achieve the step 4, overlaps can be used.
6. A horizontal ‘wrap around’ can be done for 3-variable map,
horizontal and vertical ‘wrap around’ can be done for 4-variable
map.7. Include 'don't cares' within groups as needed to achieve the
goals of point 4 above. 'Don't cares' should not be included if by so
doing the groups are not made larger or fewer.
These are six rules. Any five should be there. Each carries 2 marks.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72382
QUESTION_TEXT
Explain the recommended steps for the design of sequential
circuit.
SCHEME OF
EVALUATION
The steps are:
● Specify the problem (Word description of the circuit behavior)
● Derive the state diagram
● Obtain the state table
● The number of states may be reduced by state reduction
method
● Determine the number of flip-flops needed
● Choose the types of flip-flops to be used
● Derive excitation equation
● Using the map or any other simplification method, derive the
output function and the flip-flop input function
● Draw the logic diagram
All the steps should be given clearly.
QUESTION_TYPE DESCRIPTIVE_QUESTION
QUESTION_ID
72386
QUESTION_TEXT Briefly explain adders & subtractors with the help of truth table.
SCHEME OF
EVALUATION
Adders:
For single bit adders, there are two general types. A half adder has two
inputs, generally labeled A and B, and two outputs, the Sum S and
Carry C. S is the two bit XOR of A and B, and C is the AND of A and B.
essentially the output of a half adder is the sum of two one-bit
numbers, with C being the most significant of these two outputs. (2
marks)
A full adder has three inputs: A, B and a carry in C, such that multiple
adders can be used to add larger numbers. To remove ambiguity
between the input and output carry lines, the carry in is labeled Ci or
Cin while the carry output is labeled Co or Cout.
(2 marks)
Half adder: It is a logical circuit that performs an addition operation on
two binary digits. The half adder produces a sum and a carry value
which include both binary digits.
The drawback of this circuit is that in case of a multibit addition, it
cannot include a carry.
Logic table for half adder
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
(1 mark)
Full adder: It is a logical circuit that performs an addition operation on
three binary digits. The full adder produces a sum and carry value,
which are both binary digits. It can be combined with other full adders
or work on its own.
Input
Output
A B Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
(2 marks)
Full adder can be constructed from two half adders by connecting A
and B to the input of one half adder, connecting the sum from that to
an input to the second adder, connecting Ci to the other input and the
OR the two carry outputs. Equivalently, S could be made the three-bit
XOR of A, B and Ci and Co could be made the three-bit majority
function of A, B and Ci. The output of the full adder is the two-bit
arithmetic sum of three one-bit numbers.
(2 marks)
Subtractors:
A subtractor can be designed using the same approach as that of an
adder. The binary operation process is summarized below. As with an
adder, in the general case of calculations on multi-bit numbers, three
bits are involved in performing the subtraction for each bit: the
minuend (Xi), subtrahend (Yi) and a borrow in from the previous (less
significant) bit order position (Bi). The outputs are the difference bit
(Di) and borrow bit Bi + 1.
(3
marks)