Background Statement for
SEMI Draft Document 4578
Revision to SEMI M68-0307
PRACTICE FOR DETERMINING WAFER NEAR-EDGE GEOMETRY
FROM A MEASURED HEIGHT DATA ARRAY USING A CURVATURE
METRIC, ZDD
Notice: This background statement is not part of the balloted item. It is provided solely to assist the
recipient in reaching an informed decision based on the rationale of the activity that preceded the creation
of this document.
Notice: Recipients of this document are invited to submit, with their comments, notification of any relevant
patented technology or copyrighted items of which they are aware and to provide supporting
documentation. In this context, “patented technology” is defined as technology for which a patent has
issued or has been applied for. In the latter case, only publicly available information on the contents of the
patent application is to be provided.
The practice described in this document has been in use in the industry for several years and has
gained wide acceptance. This revision removes its Preliminary status. It also includes the
following changes to bring it up to accepted industry practice:
Clarify the use of interpolation only in placing data on sector boundaries.
Add default values for Number of Sectors and Sector Angle
Revise definitions
This letter ballot will be reviewed by the International AWG Task Force and adjudicated by the Silicon
Wafer Committee at their meetings in San Francisco, CA, during SEMICON-West, July 15-17, 2008.
Semiconductor Equipment and Materials International
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SEMI Draft Document 4578
Revision to SEMI M68-0307 PRACTICE FOR DETERMINING WAFER
NEAR-EDGE GEOMETRY FROM A MEASURED HEIGHT DATA ARRAY
USING A CURVATURE METRIC, ZDD
This standard was technically approved by the global Silicon Wafer Committee. This edition was approved
for publication by the global Audits and Reviews Subcommittee on January 18, 2007. It was available at
www.semi.org in February 2007 and on CD-ROM in March 2007.
1 Purpose
1.1 Wafer near-edge geometry can significantly affect the yield of semiconductor device processing.
1.2 Knowledge of near-edge geometrical properties can help the producer and consumer determine if the
dimensional characteristics of a specimen wafer satisfy given geometrical requirements.
1.3 The metric, ZDD, quantifies the near-edge curvature of wafers used in semiconductor device processing.
1.4 Consideration should be given to the use of this or other proposed near-edge geometry metrics as a process
control tool rather than a material exchange specification.
2 Scope
2.1 This practice covers calculation of near-edge curvature ZDD (radial double derivative of z (height)).
2.2 The metric calculated by this practice is based on a height data array; either a single surface (front or back) or
thickness.
2.3 This practice is suitable for polished, epitaxial, SOI, or other layer condition
2.4 The practice is applicable to notched 200 and 300 mm diameter wafers having dimensions in accordance with
wafer categories 1.9.2 and 1.15 of SEMI M1.
2.5 This practice does not cover acquisition of the height data array. However, it gives the required characteristics
of the height data array.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
3 Limitations
3.1 Deficiencies of data such as inadequate spatial resolution, mispositioning, noise, etc. in the height data array
used to calculate the metrics may lead to erroneous results.
3.2 Noise of the ZDD calculation may be affected by the height data array spacing and the details of the sector
averaging and the differentiation method for curvature.
4 Referenced Standards and Documents
4.1 SEMI Standards
SEMI M1 — Specifications for Polished Monocrystalline Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M59 — Terminology for Silicon Technology
SEMI M67 (Preliminary) — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data
Array Using the ESFQR and ESFQD Metrics
SEMI M69 (Preliminary) — Practice for Determining Wafer Near-Edge Geometry Using Roll-Off Amount, ROA
SEMI M70 (Preliminary) — Practice for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site
Flatness
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers
by Automated Non-Contact Scanning
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Document Number: 4578
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NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 General terms, acronyms, and symbols used in silicon wafer technology are listed and defined in SEMI M59.
5.2 Other Acronyms
5.2.1 ERO — edge roll-off.
5.2.2 ROA — edge roll off amount. (taken from M69)
5.2.3 ZDD — measure of near-edge curvature of a silicon wafer equal to the radial double derivative of the
coordinate z perpendicular to the median plane of the wafer.
5.3 Other Definitions
5.3.1 edge roll off amount (ROA) — the displacement from the reference line at the measurement point in the nearedge region of an un-chucked silicon wafer. ROA is defined as positive in the direction away from the reference
line. (modified as noted from M69)
5.3.2 edge roll-off (ERO) — surface deviations of a large-diameter silicon wafer near the edge, but excluding
effects due to wafer edge profiling and surface roughness. (modified as noted from M67)
5.3.3 near-edge geometry — the topography of a surface of a large diameter silicon wafer in the outer region of the
fixed quality area (FQA). (taken from M70)
5.3.4 sector — a portion of the outer annulus of the FQA with an angular extent in degrees equal to 360/N, where N
is the number of sectors in the annulus. (based on M67)
6 Summary of Practice
6.1 Sectors for calculation of ZDD are defined by FQA radius and sector angular extent. Required exclusions are
defined.
6.2 A height data array is acquired.
6.3 ZDD reporting radii are defined.
6.4 ZDD(r) for each sector is calculated.
6.5 Recipe parameters are reported.
6.6 ZDD is reported at the reporting radii for each sector and surface(s) analyzed.
6.7 Statistical quantities for ZDD are also calculated and reported for each wafer.
7 Apparatus
7.1 Measuring Equipment — Suitable for acquiring the height data array and transferring it to the calculation
equipment. A test method for acquiring the height data array is not covered in this document.
7.1.1 The equipment shall perform all necessary calculations and corrections needed to produce the height data
array internally and automatically, including instrument-dependent exclusion areas. The equipment shall be
equipped with a means of detecting and either deleting or identifying invalid data (over-range signal).
7.1.2 Height resolution shall be 1 nm or smaller.
7.1.3 Height data array data point spacing shall be 0.5 mm or less in two orthogonal directions in the plane of the
wafer.
7.1.4 The acquisition spatial resolution shall be appropriate for the height data array data point spacing and shall be
agreed upon between the parties of the test.
7.1.5 The height data array must cover the wafer surface including the entire FQA boundary (except in exclusion
areas).
7.1.6 Calculation Software — To perform the calculations of this practice and to provide outputs of the results,
including statistical parameters as agreed upon by the parties to the test.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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8 Procedure
8.1 Select the fixed quality area (FQA) by specifying the nominal edge exclusion EE. The FQA radius, RFQA =
RNOM – EE where RNOM is the nominal radius of the wafer (e.g., 100 or 150 mm).
8.2 Select the number of sectors, N, which defines a sector span, S =360/N. where S is in degrees .(Default N=72,
S=5 degree)
8.3 Define r1...rn as the radii for reporting of ZDD.
8.4 Determine statistics to be reported for each wafer. As a minimum, these shall include maximum, average, range,
standard deviation, and 95th percentile. Note: for small numbers of sectors (e.g., less than 100) the 95th percentile
may not be appropriate
8.5 Acquire the height data array in accordance with a method agreed upon by all parties to the practice.
9 Calculations
NOTE 1: The following calculations are performed automatically within the equipment. An outline of the calculation structures
is provided here to indicate the nature of the procedure.
NOTE 2: Data at sector boundaries is generated using interpolation.
9.1 Divide the wafer surface into N sectors, S1 to SN as follows (see Figure 1):
9.1.1 Place the outer boundary of the sectors at a radius Ro = RFQA. (see 8.1).
9.1.2 Place the counter-clockwise lateral boundary of a sector Si is at CCi = (i – 1)S + S/2.
9.1.3 Place the clockwise lateral boundary of a sector Si is at Ci = (i – 1)S – S/2.
9.2 For each sector,
9.2.1 Interpolate values from the height data array onto a polar grid having data point spacing consistent with
¶ 7.1.3 which includes the sector boundaries.
9.2.2 Calculate a sector average radial profile from the polar grid by averaging all the data within the sector and on
its boundaries at each radius.
9.2.3 Calculate ZDD(r) as the second derivative with respect to radius of the sector average radial profile.
9.3 Record ZDD(r1 ... rn).
9.4 Calculate statistics, including all quantities agreed to by the parties to the test, at each radius (r1 ... rn) for each
wafer using ZDD for each sector on the wafer.
9.5 For multi-measurement tests, calculate the standard deviations of each set of wafer measurements and such
other statistical parameters as agreed to by the parties to the test.
10 Report
10.1 Report the following information:
10.1.1 Date, time of test,
10.1.2 Identification of operator,
10.1.3 Location (laboratory) of test,
10.1.4 Identification of measuring instruments, including measuring equipment and calculation equipment
(identification of make, model, software version, etc.),
10.1.5 Acquisition Spatial Resolution and data point spacing,
10.1.6 Lot identification and wafer identification,
10.1.7 Description of sampling plan, if any,
10.1.8 FQA diameter as 2 x RFQA,
10.1.9 Sector angle, S, and
10.1.10 Data for each wafer measured, as follows:
10.1.10.1 ZDD(r1 ... rn), per sector for radii r1 ...rn
10.1.10.2 Statistics at each radius (r1 ... rn) per wafer (e.g., average, range, standard deviation, other, as agreed).
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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10.2 For multi-measurement tests, report the standard deviation of each set of wafer measurements and such other
statistical parameters as agreed to by the parties to the test.
mm
= 90o
150
150
r

50
0
Ro, c
EE
mm
100
s
= 0o
rn
125
r1
-50
-100
100
-150
-150
-100
-50
0
50
100
150
cc
101.25
mm
a. 300 mm Wafer with an EE of 3 mm with 16 Sectors
(s = 22.5°)
90
78.75
mm
b. Example of a Sector Showing the Outer Part of
Sector 5 at 90°
Figure 1
Illustration of Sectors
11 Keywords
11.1 ERO; ZDD; curvature, near-edge geometry; semiconductor; silicon; wafer
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respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
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the risk of infringement of such rights are entirely their own responsibility.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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