Background Statement for
SEMI Draft Document 4554
Revision to SEMI M67-1106
PRACTICE FOR DETERMINING WAFER NEAR-EDGE GEOMETRY
FROM A MEASURED THICKNESS DATA ARRAY USING THE ESFQR
AND ESFQD METRICS
Notice: This background statement is not part of the balloted item. It is provided solely to assist the
recipient in reaching an informed decision based on the rationale of the activity that preceded the creation
of this document.
Notice: Recipients of this document are invited to submit, with their comments, notification of any relevant
patented technology or copyrighted items of which they are aware and to provide supporting
documentation. In this context, “patented technology” is defined as technology for which a patent has
issued or has been applied for. In the latter case, only publicly available information on the contents of the
patent application is to be provided.
The practice described in this document has been in use in the industry for several years and has
gained wide acceptance. This revision removes its Preliminary status. It also includes the
following changes to bring it up to accepted industry practice:
Add the ESBIR metric to the practice.
Clarify the use of interpolation only in placing data on sector boundaries.
Add default values for Sector Length and Angle
Add definitions
This letter ballot will be reviewed by the International AWG Task Force and adjudicated by the Silicon
Wafer Committee at their meetings in San Francisco, CA, during SEMICON West July 2008.
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SEMI Draft Document 4554
Revision to SEMI M67-1106 PRACTICE FOR DETERMINING WAFER
NEAR-EDGE GEOMETRY FROM A MEASURED THICKNESS DATA
ARRAY USING THE ESFQR, ESFQD AND ESBIR METRICS
This standard was technically approved by the global Silicon Wafer Committee. This edition was approved
for publication by the global Audits and Reviews Subcommittee on August 24, 2006. It was available at
www.semi.org in October 2006 and on CD-ROM in November 2006.
1 Purpose
1.1 Wafer near-edge geometry can significantly affect the yield of semiconductor device processing.
1.2 Knowledge of near-edge geometrical properties can help the producer and consumer determine if the
dimensional characteristics of a wafer satisfy given geometrical requirements.
1.3 This practice is suitable for quantifying the flatness aspects of near-edge geometry of wafers used in
semiconductor device processing.
1.4 The ESFQR, ESFQD or ESBIR metric may be more suitable for quantifying the flatness aspects of near-edge
geometry than traditional metrics such as SFQR, SFQD or SBIR. ESFQR, ESFQD and ESBIR quantify near-edge
geometry fully and consistently at all angular positions on the wafer edge except at locations intentionally excluded.
SFQR, SFQD and SBIR, on the other hand treat different angular positions differently and do not typically provide
full coverage of the wafer edge.
NOTE 1: Acronyms beginning with E are the same as those in Appendix 1 of SEMI M1 except that they relate to the near-edge
region and have specified site dimensions.
1.5 Consideration should be given to the use of near-edge geometry metrics as a process control tool rather than a
material exchange specification.
1.6 There are other metrics for near-edge geometry, some of which quantify other aspects such as ZDD, ROA and
PSFQR
NOTE 2: ERO is frequently employed as a more general term for describing near-edge geometry, but as of the approval date of
this standard there are no standardized conditions or test procedures for it. As such a general term, ERO is included in the
keywords for this standard, even though it is outside the scope of the standard.
1.7 Other metrics analogous to flatness metrics can be calculated, but these are outside the scope of this practice.
2 Scope
2.1 This practice covers calculation of the near-edge geometry metrics ESFQR, ESFQD and ESBIR.1
2.2 The metrics calculated by this practice are based on a thickness data array. This array represents the front
surface of the wafer when the back surface of the wafer is ideally flat, as when pulled down onto an ideally clean flat
chuck.
2.3 This practice is suitable for polished, epitaxial, SOI, or other layer condition.
2.4 The practice is applicable to notched 200 and 300 mm diameter wafers having dimensions in accordance with
wafer categories 1.9.2 and 1.15 of SEMI M1.
2.5 This practice does not cover acquisition of the thickness data array. However, it gives the required
characteristics of the thickness data array.
NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the
responsibility of the users of this standard to establish appropriate safety and health practices and determine the
applicability of regulatory or other limitations prior to use.
1 The calculation of these metrics is the subject of a patent application published as US. Pub. No.US-2006-0004542 by ADE Corporation, 80
Wilson Way, Westwood, MA 02090-1806 ADE has informed SEMI that, per SEMI regulations, it will license any patent resulting from this
application on reasonable and customary terms.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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3 Limitations
3.1 Deficiencies of data such as inadequate spatial resolution, mispositioning, noise, etc. in the thickness data array
used to calculate the metrics may lead to erroneous results.
3.2 The calculations of this practice do not remove wafer shape and therefore are not applicable to data obtained
from unclamped wafer single-surface data.
3.3 The reference plane used in the calculation is dependent on both the radial length and sector span.
4 Referenced Standards and Documents
4.1 SEMI Standards
SEMI M1 — Specifications for Polished Monocrystalline Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M59 — Terminology for Silicon Technology
SEMI M68 (Preliminary) — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data
Array Using a Curvature Metric, ZDD
SEMI M69 (Preliminary) — Practice for Determining Wafer Near-Edge Geometry Using Roll-Off Amount, ROA
SEMI M70 (Preliminary) — Practice for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site
Flatness
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers
by Automated Non-Contact Scanning
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 Many terms used in silicon wafer technology are defined in SEMI M59.
5.2 Other Definitions
5.2.1 ERO — edge roll-off.
5.2.2 ESBIR — near-edge silicon wafer geometry flatness metric similar to SBIR (see Appendix 1 of SEMI M1) that
relates to the range of thickness values within a sector.
5.2.3 ESFQD — near-edge silicon wafer geometry flatness metric similar to SFQD (see Appendix 1 of SEMI M1)
that relates to the reference plane deviation having the largest absolute value within a sector while retaining the sign.
5.2.4 ESFQR — near-edge silicon wafer geometry flatness metric similar to SFQR (see Appendix 1 of SEMI M1)
that relates to the range of the reference plane deviation within a sector.
5.2.5 PSFQD — near-edge silicon wafer geometry flatness metric similar to SFQD (see Appendix 1 of SEMI M1)
except that it relates to the partial sites in the near edge region
5.2.6 PSFQR — near-edge silicon wafer geometry flatness metric similar to SFQR (see Appendix 1 of SEMI M1)
except that it relates to the partial sites in the near edge region.
5.2.7 ROA — edge roll off amount. (taken from M69)
5.2.8 ZDD — measure of near-edge curvature of a silicon wafer equal to the radial double derivative of the
coordinate z perpendicular to the median plane of the wafer.
5.2.9 edge roll off amount (ROA) — the displacement from the reference line at the measurement point in the nearedge region of an un-chucked silicon wafer. ROA is defined as positive in the direction away from the reference
line. (modified as noted from M69)
5.2.10 edge roll-off (ERO) — surface deviations of a large-diameter silicon wafer near the edge, but excluding
effects due to wafer edge profiling and surface roughness. (modified as noted from M67)
5.2.11 near-edge geometry — the topography of a surface of a large diameter silicon wafer in the outer region of
the fixed quality area (FQA). (taken from M70)
5.2.12 sector — a portion of the outer annulus of the FQA with a defined radial length and an angular extent in
degrees equal to 360/N, where N is the number of sectors in the annulus. (based on M67)
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other
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6 Summary of Practice
6.1 Sectors for metric calculation are defined by FQA radius, sector radial length and sector angular extent.
Required exclusions are defined.
6.2 A thickness data array in an annulus of defined radial length and location is acquired.
6.3 A reference plane is constructed in each sector.
6.4 ESFQR for each sector is calculated as the range of the reference plane deviation within the sector.
6.5 ESFQD for each sector is calculated as the reference plane deviation having the largest absolute value within
the sector while retaining the sign.
6.6 ESBIR for each sector is calculated as the range of thickness values within the sector.
6.7 Recipe parameters are reported.
6.8 ESFQR, ESFQD and ESBIR are reported for each sector. Statistical quantities for these parameters are also
calculated and reported for each wafer.
7 Apparatus
7.1 Measuring Equipment — Suitable for acquiring the thickness data array and transferring it to the calculation
software.
NOTE 3: A test method for acquiring a suitable thickness data array is being considered for development by the Silicon Wafer
Committee.
7.1.1 The equipment shall perform all necessary calculations and corrections needed to produce the thickness data
array internally and automatically, including instrument-dependent exclusion areas. The equipment shall be
equipped with a means of detecting and either deleting or identifying invalid data (over-range signal).
7.1.2 Thickness resolution shall be 10 nm or smaller.
7.1.3 Thickness array data point spacing shall be 0.5 mm or less in two orthogonal directions in the plane of the
wafer. The thickness data array coordinate system is per SEMI M20.
7.1.4 The spatial resolution of the thickness data array shall be specified.
7.1.5 The thickness data array must cover an annulus including the entire FQA boundary (except in exclusion areas)
and the inner boundary of the sector annulus (see ¶ 9.1.2).
7.2 Calculation Software — To perform the calculations of this practice and to provide outputs of the results,
including statistical parameters as agreed upon by the parties to the test.
8 Procedure
8.1 Define recipe for calculation:
8.1.1 Select the fixed quality area (FQA) by specifying the nominal edge exclusion EE. The FQA radius,
RFQA = RNOM – EE where RNOM is the nominal radius of the wafer (e.g., 100mm or 150mm).
8.1.2 Select the sector radial length, LR (default = 30mm).
8.1.3 Select the number of sectors, N, which defines a sector span, S = 360/N, where S is in degrees .(Default
N=72, S=5 degree)
8.1.4 Determine statistics to be reported for each wafer. As a minimum, these shall include maximum, average,
range, standard deviation and 95th percentile,
NOTE 4:For small numbers of sectors (e.g., less than 100) the 95th percentile may not be appropriate.
8.2 Acquire the thickness data array in accordance with a method agreed upon by all parties to the practice (see
Note 3).
9 Calculations
NOTE 5: The following calculations are performed automatically within the calculation equipment.
calculation structures is provided here to indicate the nature of the procedure.
An outline of the
9.1 Construct an annulus divided into N sectors, S1 to SN on the wafer front surface as follows (see Figure 1):
9.1.1 Place the outer boundary of the annulus at a radius Ro = RFQA (see ¶ 8.1.1).
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
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9.1.2 Place the inner boundary of the annulus at a radius Ri = RFQA – LR.
9.1.3 Place the counter-clockwise lateral boundary of sector Si at cci = (i – 1)S + S/2.
9.1.4 Place the clockwise lateral boundary of sector Si at ci = (i – 1)S – S/2.
9.2 For each sector:
9.2.1 Calculate thickness data values along all sector boundaries based on values from the thickness data array.
NOTE 6: Data at sector boundaries is generated using interpolation .
9.2.2 Construct a front surface least-squares reference plane from all the data within the sector and on its boundaries.
9.2.3 Determine the most positive dmax and the most negative dmin differences between the thickness data array
values and the reference plane within the sector and at the sector boundaries.
9.2.4 Record ESFQR for the sector as |dmax| + |dmin| (peak-to-valley).
9.2.5 Record ESFQD for the sector as the larger of |dmax| or |dmin|, maintaining the sign of the original deviation.
9.2.6 Determine the maximum,, Tmax and minimum Tmin thickness data array values within the sector and at the
sector boundaries.
9.2.7 Record ESBIR for the sector as T max – Tmin (peak-to-valley).
9.2.8 Calculate statistics for each wafer using ESFQR and ESFQD for each sector on the wafer.
9.3 For tests where the wafer is measured more than once, calculate the maximum, minimum, sample standard
deviation, average, and range of all individual sectors on the wafer.
9.4 Record sample standard deviation and other statistical parameters as agreed upon between the parties to the test.
10 Report
10.1 Report the following information:
10.1.1 Date, time of test,
10.1.2 Identification of operator,
10.1.3 Location (laboratory) of test,
10.1.4 Identification of measuring instruments, including measuring equipment and calculation equipment
(identification of make, model, software version, etc.).
10.1.5 Acquisition Spatial Resolution and data point spacing.
10.1.6 Lot identification and wafer identification,
10.1.7 Description of sampling plan, if any, and
10.1.8 Data for each wafer measured.
10.1.8.1 ESFQR:
10.1.8.1.1 Per sector, and
10.1.8.1.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.1.8.2 ESFQD:
10.1.8.2.1 Per sector, and
10.1.8.3 Statistics per wafer (e.g., average, range, standard deviation, other). ESBIR:
10.1.8.3.1 Per sector, and
10.1.8.3.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.1.8.4 Recipe:
10.1.8.4.1 FQA diameter,
10.1.8.4.2 Radial length, LR, and
10.1.8.4.3 Sector angle, S.
10.2 For multi-measurement tests the report shall also include the standard deviation of each set of wafer
measurements and such other statistical parameters as have been agreed to by the parties to the test.
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
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R o,  c
EE
= 90o

s
r
= 0o
LR
97.5
95
92.5
90
87.5
85
82.5
Ri, cc
a. 300 mm wafer with an EE of 2 mm with 72
sectors (s = 5°) and a radial length (LR) = 30 mm
b. An example of a sector showing the sector at
90°
NOTE: The coordinate system associated with the sector configuration is consistent with the wafer coordinate
system of SEMI M20.
Figure 1
Illustration of Sectors and Detail of a Sector
11 Keywords
11.1 ERO; ESFQR; ESFQD, ESBIR; edge rolloff, near-edge geometry; semiconductor; silicon; wafer
This is a draft document of the SEMI International Standards program. No material on this page is to be construed as an offi cial or adopted standard. Permission is granted to
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