Background Statement for SEMI Draft Document 5705
REVISION OF SEMI M67-1109 With Title Change To:
TEST METHOD FOR DETERMINING WAFER NEAR-EDGE GEOMETRY
FROM A MEASURED THICKNESS DATA ARRAY USING THE ESFQR,
ESFQD AND ESBIR METRICS
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in
reaching an informed decision based on the rationale of the activity that preceded the creation of this document.
Notice: Recipients of this document are invited to submit, with their comments, notification of any relevant patented
technology or copyrighted items of which they are aware and to provide supporting documentation. In this context,
“patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter
case, only publicly available information on the contents of the patent application is to be provided.
SEMI Standard M67 has long been improperly titled to be a Practice. The latest edition of the SEMI Regulations
defines Practice and Test Method as follows:


4.2.24.4 Practice, n — A Subtype of Standard providing a definitive procedure for performing one or more
specific operations or functions that does not produce a test result. (Compare Test Method.)
4.2.24.7 Test Method, n — A Subtype of Standard providing a definitive procedure for the identification,
measurement, and evaluation of one or more qualities, characteristics, or properties of a material, product,
system, or service that produces a test result. (Compare Practice.)
From this it can be seen that the document is clearly a Test Method, not a Practice. Since the Standard is actually
written in the form of a test method, the only changes are to replace the term “Practice” with “Test Method” where
appropriate.
In addition, Section 2.4 of Scope no longer enumerates the applicable M1 wafer categories, instead making a
general statement.
The reference in Section 4.1 to SEMI M69 (Preliminary) — Practice for Determining Wafer Near-Edge Geometry
Using Roll-Off Amount, ROA is obsolete. It is replaced by SEMI M77 — Practice for Determining Wafer NearEdge Geometry Using Roll-Off Amount, ROA.
Notice: Additions are indicated by underline and deletions are indicated by strikethrough.
Review and Adjudication Information
Group:
Date:
Time & Timezone:
Location:
City, State/Country:
Leader(s):
Standards Staff:
Task Force Review
Int’l Advanced Wafer Geometry TF
Monday, July 13, 2015
2:00 PM -5:00 PM PDT
San Francisco Marriott Marquis
San Francisco, CA USA
Jaydeep Sinha (KLA-Tencor)
Noel Poduje (SMS)
Kevin Nguyen, knguyen@semi.org
Committee Adjudication
NA Silicon Wafer TC Chapter
Tuesday, July 14, 2015
1:00 PM -4:00 PM PDT
San Francisco Marriott Marquis
San Francisco, CA USA
Noel Poduje (SMS)
Dinesh Gupta
Kevin Nguyen, knguyen@semi.org
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact the task
force leaders or Standards staff for confirmation.
Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to
attend these meetings in person but would like to participate by telephone/web, please contact Standards staff.
Check www.semi.org/standards on calendar of event for the latest meeting schedule.
Semiconductor Equipment and Materials International
3081 Zanker Road
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Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
Document Number: 5705
Date: 2/16/2016
REVISION OF SEMI M67-1109 With Title Change To:
TEST METHOD FOR DETERMINING WAFER NEAR-EDGE GEOMETRY
FROM A MEASURED THICKNESS DATA ARRAY USING THE ESFQR,
ESFQD AND ESBIR METRICS
1 Purpose
1.1 Wafer near-edge geometry can significantly affect the yield of semiconductor device processing.
1.2 Knowledge of near-edge geometrical properties can help the producer and consumer determine if the
dimensional characteristics of a wafer satisfy given geometrical requirements.
1.3 This test method is suitable for quantifying the flatness aspects of near-edge geometry of wafers used in
semiconductor device processing.
1.4 The ESFQR, ESFQD or ESBIR metric may be more suitable for quantifying the flatness aspects of near-edge
geometry than traditional metrics such as SFQR, SFQD or SBIR. ESFQR, ESFQD and ESBIR quantify near-edge
geometry fully and consistently at all angular positions on the wafer edge except at locations intentionally excluded.
SFQR, SFQD and SBIR, on the other hand treat different angular positions differently and do not typically provide
full coverage of the wafer edge.
NOTE 1: Acronyms beginning with E are analogous to those in Appendix 1 of SEMI M1 but relate to the near-edge region. The
letter “S” in these acronyms refers to an edge Sector rather than to an exposure Site.
1.5 Consideration should be given to the use of near-edge geometry metrics as a process control tool rather than a
material exchange specification.
1.6 There are other metrics for near-edge geometry, some of which quantify other aspects such as ZDD, ROA and
PSFQR.
NOTE 2: ERO is frequently employed as a more general term for describing near-edge geometry, but as of the approval date of
this standard there are no standardized conditions or test procedures for it. As such a general term, ERO is included in the
keywords for this standard, even though it is outside the scope of the standard.
2 Scope
2.1 This test method covers calculation of the near-edge geometry metrics ESFQR, ESFQD and ESBIR. 1
2.2 The metrics calculated by this test method are based on a thickness data array. This array represents the front
surface of the wafer when the back surface of the wafer is ideally flat, as when pulled down onto an ideally clean flat
chuck.
2.3 This test method is suitable for polished, epitaxial, SOI, or other layer condition.
2.4 The test method is applicable to categories of wafers specified in SEMI M1 used in advanced IC manufacturing.
2.5 This test method does not cover acquisition of the thickness data array. However, it gives the required
characteristics of the thickness data array.
2.6 Other metrics analogous to flatness metrics can be calculated, but these are outside the scope of this test method.
NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their
use. It is the responsibility of the users of the documents to establish appropriate safety and health practices, and
determine the applicability of regulatory or other limitations prior to use.
1 The calculation of these metrics is the subject of U.S. Patent 7,324,917 owned by KLA-Tencor Corporation, One Technology Drive, Milpitas,
CA 95035. KLA-Tencor has informed SEMI that, per SEMI regulations, it will license this patent on reasonable and customary terms.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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LETTER BALLOT
SEMI Draft Document 5705
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
Document Number: 5705
Date: 2/16/2016
3.1 Deficiencies of data such as inadequate spatial resolution, mispositioning, noise, etc. in the thickness data array
used to calculate the metrics may lead to erroneous results.
3.2 The calculations of this test method do not remove wafer shape and therefore are not applicable to data obtained
from unclamped wafer single-surface data.
3.3 The reference plane used in the calculation is dependent on both the radial length and sector span.
4 Referenced Standards and Documents
4.1 SEMI Standards
SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M59 — Terminology for Silicon Technology
SEMI M68 — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a
Curvature Metric, ZDD
SEMI M70 — Practice for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site Flatness
SEMI M77 — Practice for Determining Wafer Near-Edge Geometry Using Roll-Off Amount, ROA
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers
by Automated Non-Contact Scanning
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 Acronyms, terms, and symbols used in silicon wafer technology, including those in this test method, are given
in SEMI M59.
6 Summary of Test Method
6.1 Sectors for metric calculation are defined by FQA radius, sector radial length and sector angular extent.
Required exclusions are defined.
6.2 A thickness data array in an annulus of defined radial length and location is acquired.
6.3 A reference plane is constructed in each sector.
6.4 ESFQR for each sector is calculated as the range of the reference plane deviation within the sector.
6.5 ESFQD for each sector is calculated as the reference plane deviation having the largest absolute value within
the sector while retaining the sign.
6.6 ESBIR for each sector is calculated as the range of thickness values within the sector.
6.7 Recipe parameters are reported.
6.8 ESFQR, ESFQD and ESBIR are reported for each sector. Statistical quantities for these parameters are also
calculated and reported for each wafer.
7 Apparatus
7.1 Measuring Equipment — Suitable for acquiring the thickness data array and transferring it to the calculation
software.
NOTE 3: A test method for acquiring a suitable thickness data array is being considered for development by the Silicon Wafer
Committee.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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3 Limitations
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7.1.1 The equipment shall perform all necessary calculations and corrections needed to produce the thickness data
array internally and automatically, including instrument-dependent exclusion areas. The equipment shall be
equipped with a means of detecting and either deleting or identifying invalid data (over-range signal).
7.1.2 Thickness resolution shall be 10 nm or smaller.
7.1.3 Thickness array data point spacing shall be 0.5 mm or less in two orthogonal directions in the plane of the
wafer. The thickness data array coordinate system is per SEMI M20.
7.1.4 The spatial resolution of the thickness data array shall be specified.
7.1.5 The thickness data array must cover an annulus including the entire FQA boundary (except in exclusion areas)
and the inner boundary of the sector annulus (see ¶ 9.1.2).
7.2 Calculation Software — To perform the calculations of this test method and to provide outputs of the results,
including statistical parameters as agreed upon by the parties to the test.
8 Procedure
8.1 Define recipe for calculation:
8.1.1 Select the fixed quality area (FQA) by specifying the nominal edge exclusion EE. The FQA radius,
RFQA = RNOM – EE where RNOM is the nominal radius of the wafer (e.g., 100 mm or 150 mm).
8.1.2 Select the sector radial length, LR (default = 30 mm).
8.1.3 Select the number of sectors, N, which defines a sector span, S = 360/N, where S is in degrees (Default N=72,
S=5 degree).
8.1.4 Determine statistics to be reported for each wafer. As a minimum, these shall include maximum, average,
range, standard deviation and 95th percentile.
NOTE 4: For small numbers of sectors (e.g., less than 100) the 95th percentile may not be appropriate.
8.2 Acquire the thickness data array in accordance with a method agreed upon by all parties to the test method (see
Note 3).
9 Calculations
NOTE 5: The following calculations are performed automatically within the calculation equipment. An outline of the calculation
structures is provided here to indicate the nature of the procedure.
9.1 Construct an annulus divided into N sectors, S1 to SN on the wafer front surface as follows (see Figure 1):
9.1.1 Place the outer boundary of the annulus at a radius Ro = RFQA (see ¶ 8.1.1).
9.1.2 Place the inner boundary of the annulus at a radius Ri = RFQA – LR.
9.1.3 Place the counter-clockwise lateral boundary of sector Si at cci = (i – 1)S + S/2.
9.1.4 Place the clockwise lateral boundary of sector Si at ci = (i – 1)S – S/2.
9.2 For each sector:
9.2.1 Calculate thickness data values along all sector boundaries based on values from the thickness data array.
NOTE 6: Data at sector boundaries is generated using interpolation.
9.2.2 Construct a front surface least-squares reference plane from all the data within the sector and on its boundaries.
9.2.3 Determine the most positive dmax and the most negative dmin differences between the thickness data array
values and the reference plane within the sector and at the sector boundaries.
9.2.4 Record ESFQR for the sector as |dmax| + |dmin| (peak-to-valley).
9.2.5 Record ESFQD for the sector as the larger of |dmax| or |dmin|, maintaining the sign of the original deviation.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Document Number: 5705
Date: 2/16/2016
Semiconductor Equipment and Materials International
3081 Zanker Road
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Phone: 408.943.6900, Fax: 408.943.7943
9.2.6 Determine the maximum, Tmax and minimum Tmin thickness data array values within the sector and at the
sector boundaries.
9.2.7 Record ESBIR for the sector as T max – Tmin (peak-to-valley).
9.2.8 Calculate statistics for each wafer using ESFQR and ESFQD for each sector on the wafer.
9.3 For tests where the wafer is measured more than once, calculate the maximum, minimum, sample standard
deviation, average, and range of all individual sectors on the wafer.
9.4 Record sample standard deviation and other statistical parameters as agreed upon between the parties to the test.
10 Report
10.1 Report the following information:
10.1.1 Date, time of test,
10.1.2 Identification of operator,
10.1.3 Location (laboratory) of test,
10.1.4 Identification of measuring instruments, including measuring equipment and calculation equipment
(identification of make, model, software version, etc.).
10.1.5 Acquisition Spatial Resolution and data point spacing.
10.1.6 Lot identification and wafer identification,
10.1.7 Description of sampling plan, if any, and
10.1.8 Data for each wafer measured.
10.1.8.1 ESFQR:
10.1.8.1.1 Per sector, and
10.1.8.1.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.1.8.2 ESFQD:
10.1.8.2.1 Per sector, and
10.1.8.2.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.1.8.3 ESBIR:
10.1.8.3.1 Per sector, and
10.1.8.3.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.1.8.4 Recipe:
10.1.8.4.1 FQA diameter as 2 × RFQA,
10.1.8.4.2 Radial length, LR, and
10.1.8.4.3 Sector angle, S.
10.2 For multi-measurement tests the report shall also include the standard deviation of each set of wafer
measurements and such other statistical parameters as have been agreed to by the parties to the test.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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DRAFT
Document Number: 5705
Date: 2/16/2016
Semiconductor Equipment and Materials International
3081 Zanker Road
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Phone: 408.943.6900, Fax: 408.943.7943
mm
Ro, c19
EE
= 90o

mm
s
r
= 0o
LR
97.5
95
92.5
90
87.5
85
82.5
mm
mm
Ri, cc19
a. 300 mm wafer with an EE of 2 mm with 72
sectors (s = 5°) and a radial length (LR) = 30 mm
b. An example of a sector showing the sector at
90°
NOTE: The coordinate system associated with the sector configuration
is consistent with the wafer coordinate system of SEMI M20.
Figure 1
Illustration of Sectors and Detail of a Sector
11 Keywords
11.1 ERO; ESFQR; ESFQD, ESBIR; edge rolloff, near-edge geometry; semiconductor; silicon; wafer
NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for
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user. Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other
relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change
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The user’s attention is called to the possibility that compliance with this standard may require use of copyrighted
material or of an invention covered by patent rights. KLA-Tencor Corporation has filed a statement with SEMI
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This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
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Document Number: 5705
Date: 2/16/2016