Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this document.
Notice: Recipients of this document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context,
“patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.
SEMI Standard M70 has long been improperly titled to be a Practice. The latest edition of the SEMI Regulations defines Practice and Test Method as follows:

4.2.24.4 Practice, n — A Subtype of Standard providing a definitive procedure for performing one or more specific operations or functions that does not produce a test result. (Compare Test Method.)

4.2.24.7 Test Method, n — A Subtype of Standard providing a definitive procedure for the identification, measurement, and evaluation of one or more qualities, characteristics, or properties of a material, product, system, or service that produces a test result. (Compare Practice.)
From this it can be seen that the document is clearly a Test Method, not a Practice. Since the Standard is actually written in the form of a test method, the only changes are to replace the term “Practice” with “Test Method” where appropriate.
In addition, Section 2.5 of Scope no longer enumerates the applicable M1 wafer categories, instead making a general statement.
Notice: Additions are indicated by underline and deletions are indicated by strikethrough .
Review and Adjudication Information
Group:
Date:
Task Force Review
Int’l Advanced Wafer Geometry TF
Monday, July 13, 2015
Time & Timezone: 2:00 PM -5:00 PM PDT
Location: San Francisco Marriott Marquis
City, State/Country: San Francisco, CA USA
Leader(s): Frank Riedel (Siltronic AG)
Jaydeep Sinha (KLA-Tencor)
Noel Poduje (SMS)
Masanori Yoshise
Satoshi Akiyama (Raytex)
Committee Adjudication
NA Silicon Wafer TC Chapter
Tuesday, July 14, 2015
1:00 PM -4:00 PM PDT
San Francisco Marriott Marquis
San Francisco, CA USA
Noel Poduje (SMS)
Dinesh Gupta
Standards Staff: Kevin Nguyen, knguyen@semi.org
Kevin Nguyen, knguyen@semi.org
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact the task force leaders or Standards staff for confirmation.
Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to attend these meetings in person but would like to participate by telephone/web, please contact Standards staff.
Check www.semi.org/standards on calendar of event for the latest meeting schedule.

Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
Document Number: 5706
Date: 11.04.2020
1 Purpose
1.1 Wafer near edge geometry can significantly affect the yield of semiconductor device processing.
1.2 Knowledge of near edge geometrical properties can help the producer and consumer to determine if the dimensional characteristics of a wafer satisfy given geometrical requirements.
1.3 This practice test method is suitable quantifying the near edge geometry of wafers used in semiconductor device processing.
1.4 The PSFQR or PSFQD metric is suitable for quantifying near edge geometry when applying a site pattern that appropriately covers large parts of the wafer edge.
NOTE 1: Acronyms beginning with P are the same as those in Appendix 1 of SEMI M1 except that they relate to the partial sites covering the near edge region.
1.5 Flatness metric is well-established therefore partial site flatness can be used as a process control tool as well as a material exchange specification for edge geometry.
1.6 There are other metrics i.e., ZDD, ESFQR, ROA, some of which quantify more specific aspects of edge geometry.
NOTE 2: ERO is frequently employed as a more general term for describing near edge geometry, but as of the approval date of this standard there are no standardized conditions or test procedures for it. As such a general term, ERO is included in the keywords for this standard, even though it is outside the scope of the standard.
2 Scope
2.1 This practice test method covers calculation of the near edge geometry metrics PSFQR and PSFQD.
2.2 SFQR and SFQD are well known parameters and described in detailed in SEMI MF1530. In contrast to
SEMI MF1530 the present practice test method is dealing exclusively with the non-full sites (i.e., the partial sites).
The practice test method is focused only and specifically on near edge geometry applications.
2.3 The metrics calculated by this practice test method are based on a thickness data array (see also SEMI MF1530).
This array represents the front surface of the wafer when the back surface of the wafer is ideally flat, as when pulled down onto an ideally clean flat chuck.
2.4 This practice test method is suitable for polished, epitaxial, SOI, or other layer condition.
2.5 The practice test method is applicable to notched 200 and 300 mm diameter wafers having dimensions in accordance with wafer categories 1.9.2, 1.9.3, 1.15, and 1.15.1 of SEMI M1 categories of wafers specified in SEMI
M1 used in advanced IC manufacturing .
2.6 This practice test method does not cover acquisition of the thickness data array. However, it gives the required characteristics of the thickness data array.
NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use. It is the responsibility of the users of the documents to establish appropriate safety and health practices, and determine the applicability of regulatory or other limitations prior to use.
3 Limitations
3.1 Deficiencies of data such as inadequate spatial resolution, mispositioning, noise, etc. in the thickness data array used to calculate the metrics may lead to erroneous results.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 1 Doc. 5706
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Semiconductor Equipment and Materials International obtained from unclamped wafer single-surface data.
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3.2 The calculations of this practice test method do not remove wafer shape and therefore are not applicable to data
Document Number: 5706
Date: 11.04.2020
3.3 The reference plane used in the calculation is dependent on the x - and y -length of the sites and the x - and y -offset of the site pattern.
4 Referenced Standards and Documents
4.1 SEMI Standards
SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M49 — Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 22 nm
Technology Generations
SEMI M59 — Terminology for Silicon Technology
SEMI M67 — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR and ESFQD Metrics
SEMI M68 — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a
Curvature Metric, ZDD
SEMI M69 (Preliminary) — Practice Test Method for Determining Wafer Near-Edge Geometry Using Roll-Off
Amount, ROA
SEMI M77 — Practice Test Method for Determining Wafer Near-Edge Geometry Using Roll-Off Amount, ROA
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Non-Contact Scanning
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 Acronyms, terms, and symbols used in silicon wafer technology, including those in this practice test method , are given in SEMI M59.
6 Summary of Practice Test Method
6.1 All partial sites are used for metric calculation. Partial sites are defined by FQA, the site size and offset.
Required exclusions are defined.
6.2 A thickness data array is acquired.
6.3 The data array is used to construct a reference plane in each site.
6.4 PSFQR for each site is calculated as the range of the reference plane deviation within the site.
6.5 PSFQD for each site is calculated as the reference plane deviation within the site having the largest absolute value within the site while retaining the sign.
6.6 Recipe parameters are reported.
6.7 PSFQR and PSFQD are reported for each site. Statistical quantities for these parameters are also calculated and reported for each wafer.
7 Apparatus
7.1 Measuring Equipment — Suitable for acquiring the thickness data array and transferring it to the calculation software.
NOTE 3: A test method for acquiring a suitable thickness data array is being considered for development by the Silicon Wafer
Committee.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Semiconductor Equipment and Materials International
3081 Zanker Road
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DRAFT
Document Number: 5706
Date: 11.04.2020
Phone: 408.943.6900, Fax: 408.943.7943
7.1.1 The equipment shall perform all necessary calculations and corrections needed to produce the thickness data array internally and automatically, including instrument-dependent exclusion areas. The equipment shall be equipped with a means of detecting and either deleting or identifying invalid data (over-range signal).
7.1.2 Thickness resolution shall be 10 nm or smaller.
7.1.3 Thickness array data point spacing shall be 1 mm or less in two orthogonal directions in the plane of the wafer.
The thickness data array coordinate system is per SEMI M20.
7.1.4 The spatial resolution of the thickness data array shall be specified.
7.1.5 The thickness data array must cover the entire area of the partial sites including the FQA boundary (except in exclusion areas).
7.2 Calculation Software — To perform the calculations of this practice test method and to provide outputs of the results, including statistical parameters as agreed upon by the parties to the test method.
8 Procedure
8.1 Define recipe for calculation:
8.1.1 Select the fixed quality area (FQA) by specifying the nominal edge exclusion EE. The FQA radius,
R
FQA
= R
NOM
– EE .
8.1.2 Select the site length L x
and length L y
. Recommended site lengths are: L x
= L y
= 20 mm.
8.1.3 Select the site pattern’s x -offset OS x
and y -offset OS y
.
8.1.4 Construct a site pattern with N partial sites on the wafer front surface (see Figure 1).
8.2 Determine statistics to be reported for each wafer. As a minimum, these shall include maximum, average, range, standard deviation, and 95 th percentile and any other statistics agreed upon between parties to the test. Acquire the thickness data array in accordance with a method agreed upon by all parties to the practice test method (see Note 3).
9 Calculations
NOTE 4: The following calculations are performed automatically within the calculation equipment. An outline of the calculation structures is provided here to indicate the nature of the procedure.
9.1 For each site,
9.2 Generate thickness data for all partial sites based on values from the thickness data array.
9.3 Construct a front surface least-squares reference plane from all the data within the partial site.
9.4 Determine the most positive d max
and the most negative d min
differences between the thickness data array values and the reference plane within the partial site.
9.5 Record PSFQR for the partial site as | d max
| + | d min
| (peak-to-valley).
9.6 Record PSFQD for the partial site as the larger of | d max
| or | d min
|, maintaining the sign of the original deviation.
9.7 Calculate statistics for each wafer using PSFQR and PSFQD for each partial site on the wafer.
9.8 For tests where the wafer is measured more than once, calculate the maximum, minimum, sample standard deviation, average, and range of all individual partial sites on the sample.
9.9 Record sample standard deviation and other statistical parameters as agreed upon between the parties to the practice test method .
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
Document Number: 5706
Date: 11.04.2020
NOTE 1: Recommended partial site pattern on a 300 mm wafer front surface providing 32 partial sites (dark grey color) at FQA radius R
FQA
= 149 mm, for calculating
PSFQR and PSFQD (site lengths L x
= L y
= 20 mm and x-offset OS x
= y-offset OS y
= 10 mm).
NOTE 2: The coordinate system associated with the sector configuration is consistent with the wafer coordinate system of SEMI M20.
Figure 1
Illustration of Partial Sites
10 Report
10.1 Report the following information:
10.2 Date, time of test,
10.3 Identification of operator,
10.4 Location (laboratory) of test,
10.5 Identification of measuring instruments including measuring equipment and calculation equipment
(identification of maker, model, software version, etc.),
10.6 Acquisition Spatial Resolution and data point spacing,
10.7 Lot identification and wafer identification,
10.8 Description of sampling plan, if any and
10.9 Recipe:
10.9.1 FQA diameter,
10.9.2 Site length, L x
, L y and
10.9.3 Site pattern offset, OS x
, OS y
.
10.10 Data for each wafer measured.
10.10.1 PSFQR:
10.10.1.1 Per partial site, and
10.10.1.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.10.2 PSFQD:
10.10.2.1 Per partial site, and
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Semiconductor Equipment and Materials International DRAFT
3081 Zanker Road
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Document Number: 5706
Date: 11.04.2020
Phone: 408.943.6900, Fax: 408.943.7943
10.10.2.2 Statistics per wafer (e.g., average, range, standard deviation, other).
10.11 For multi-measurement tests the report shall also include the standard deviation of each set of wafer measurements and such other statistical parameters as have been agreed to by the parties to the test.
11 Keywords
11.1 ERO; PSFQD; PSFQD; near edge geometry; semiconductor; silicon; wafer
NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the user. Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change without notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
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