ELEN 468
Advanced Logic Design
Lecture 24
Design for Testability
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Test Cost
Test pattern generation
Fault simulation
Generation of fault sites information
Test equipment
Test process
Test cost may overweight design cost
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Why Design for Testability?
Testability is a design characteristic that
influences various costs associated with
testing
It allows for
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Device status to be determined
Isolation of faults
Reduce test time and cost
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Controllability
Ability to establish a specific signal
value at each node by setting circuit’s
inputs
Circuits typically difficult to control:
decoders, circuits with feedback,
oscillators, clock generators …
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Observability
Ability to determine the signal value at
any node in a circuit by controlling the
circuit’s inputs and observing its output
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Predictability
Ability to obtain known output values in
response to given input stimuli
Factors affecting predictability
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Initial state of circuit
Races
Hazards
……
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Difficult Test Cases
Sequential logic is more difficult to test
than combinational logic
Control logic is more difficult to test
than data-path logic
Random logic is more difficult to test
than structured bus-oriented designs
Asynchronous design is more difficult to
test than synchronous design
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Quantify Testability
Need approximate measure of:

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Difficulty of setting internal circuit lines to 0 or 1
by setting primary circuit inputs
Difficulty of observing internal circuit lines by
observing primary outputs
Uses:
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Analysis of difficulty of testing internal circuit parts
– redesign or add special test hardware
Guidance for algorithms computing test patterns –
avoid using hard-to-control lines
Estimation of fault coverage
Estimation of test vector length
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Types of Measures



SCOAP – Sandia Controllability and Observability
Analysis Program
Combinational measures:
 CC0 – Difficulty of setting circuit line to logic 0
 CC1 – Difficulty of setting circuit line to logic 1
 CO – Difficulty of observing a circuit line
Sequential measures – analogous:
 SC0
 SC1
 SO
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Range of SCOAP Measures
 Controllabilities – 1 (easiest) to infinity (hardest)
 Observabilities – 0 (easiest) to infinity (hardest)
 Combinational measures:

Roughly proportional to # circuit lines that must be
set to control or observe given line
 Sequential measures:

Roughly proportional to # times a flip-flop must be
clocked to control or observe given line
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Controllability Examples
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Observability Examples
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Goal of Design for Testability (DFT)
Improve
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Controllability
Observability
Predictability
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Design and Test Trade-off
Most DFT ( Design for Testability )
techniques need extra hardware, or
modification to circuits that may affect
performances
DFT need to consider the cost trade-off
between design and test
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DFT Methods
DFT methods for digital circuits:


Ad-hoc methods
Structured methods:
 Scan
 Partial Scan
 Built-in self-test (BIST)
 Boundary scan
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Ad-Hoc DFT Methods
Good design practices learnt through experience are used as
guidelines:
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Avoid asynchronous (unclocked) feedback
Make flip-flops initializable
Avoid redundant gates
Avoid large fanin gates
Provide test control for difficult-to-control signals
Avoid gated clocks
Design reviews conducted by experts or design auditing tools
Disadvantages of ad-hoc DFT methods:
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Experts and tools not always available
Test generation is often manual with no guarantee of high fault
coverage
Design iterations may be necessary
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Scan Design
Circuit is designed using pre-specified design
rules
Test structure (hardware) is added to the
verified design:
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Add a test control (TC) primary input
Replace flip-flops by scan flip-flops (SFF) and
connect to form one or more shift registers in the
test mode
Make input/output of each scan shift register
controllable/observable from PI/PO
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Scan Design Rules
Use only clocked D-type of flip-flops for
all state variables
At least one PI pin must be available for
test; more pins, if available, can be used
All clocks must be controlled from PIs
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Correcting a Rule Violation
All clocks must be controlled from PIs
Comb.
logic D1
Q
Comb.
logic
FF
D2
CK
Comb.
logic
D1
D2
CK
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FF
Comb.
logic
19
Scan Storage Cell
D
Si
N/T’
Clk
Q, So
SSC
SSC
D
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Scan Flip-Flop (SFF)
Master latch
D
N/T’
Slave latch
Q
Logic
overhead
Si
MUX
Q
Clk
D flip-flop
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Scan Methods
C1
C2
C1
MUX
C2
Si
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Boundary Scan
MUX
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Integrated Serial Scan
PI
PO
Combinational
SFF
logic
SFF
SCANOUT
SFF
Control
SCANIN
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