ELEN 468
Advanced Logic Design
Lecture 25
Built-in Self Test
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BIST ( Built-in Self Test )
PRPG: Pseudo Random Pattern Generator
ORA: Output Response Analyzer
CUT: Circuit Under Test
Start
PRPG
PI
CUT
PO
ORA
Pass/fail
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BIST Motivation
Useful for field test and diagnosis (less
expensive than a local automatic test
equipment)
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Benefits and Costs of BIST
Level
Design
and test
Fabri- Manuf. Maintenance Diagnosis
Service
and repair interruption
cation Test
test
Chips
+/-
+
-
Boards
+/-
+
-
System
+/-
+
-
-
-
-
+ Cost increase
- Cost saving
+/- Cost increase may balance cost reduction
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Economics – BIST Costs

Chip area overhead for:







Test controller
Hardware pattern generator
Hardware response compacter
Testing of BIST hardware
Pin overhead – at least 1 pin needed to activate
BIST operation
Performance overhead – extra path delays
Reliability reduction – due to increased area
and complexity
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BIST Benefits
 Reduced testing and maintenance cost
 Lower test generation cost
 Reduced storage / maintenance of test
patterns
 Simpler and less expensive ATE
 Can test many units in parallel
 Shorter test application times
 Can test at functional system speed
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BIST Types
On-line BIST


Concurrent
Non-concurrent
Off-line BIST


Functional
Structural
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BIST Architecture
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Pseudo-Random Pattern
Generation through LFSR
Linear Feedback Shift Register (LFSR)
 Produces patterns algorithmically – repeatable
 Has most of desirable random # properties
Long sequences needed for good fault coverage
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Response Compaction
Severe amounts of data in CUT response
to LFSR patterns – example:
 Generate 5 million random patterns
 CUT has 200 outputs
 5 million x 200 = 1 billion bits response
Uneconomical to store and check all of
these responses on chip
Responses must be compacted
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LFSR for Response Compacter
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Signature Analysis
Signature – any statistical circuit property
distinguishing between bad and good circuits
Aliasing – due to information loss, signatures
of good and some bad machines match
Signature analysis – compare good machine
response into good machine signature. Actual
signature generated during testing, and
compared with good machine signature
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BILBO
(Built-in Logic Block Observer)
Four modes:
1.
2.
3.
4.
Flip-flop
LFSR pattern generator
LFSR response compacter
Scan chain for flip-flops
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Example of BILBO
Combined functionality of D flip-flop, pattern
generator, response compacter and scan chain
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BILBO Serial Scan Mode
B1 B2 = “00”
Dark lines show enabled data paths
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BILBO LFSR Pattern Generator Mode
B1 B2 = “01”
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BILBO in D-FF (Normal) Mode
B1 B2 = “10”
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BILBO in Response Compactor Mode
B1 B2 = “11”
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Exercises 7
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Problem 1
always @ ( … ) begin
for ( j = 0; j < n; j = j + 1 )
begin
a[j] = 0;
for ( k = 0; k < j; k = k + 1 )
@ ( posedge clock )
a[j] = a[j] + x[k];
end
end
always @ ( … ) begin
…
a[0] = 0;
for ( j = 0; j < n; j = j + 1 )
begin
@ ( posedge clock )
a[j] = a[j-1] + x[j-1];
end
end
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Problem 2
clock
a
x
Flip-flop
y
b
c
Latch
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Problem 3.1
Reg b
Reg a
Reg c
+
+
+
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Problem 3.2
Reg b
Reg a
Reg c
+
+
+
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