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Today’s class
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Digital Logic
Friday, October 19, 2007
Computer Architecture I - Class 8
1
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Digital circuits
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Two logical values
 Binary
0 (signal between 0 and 1 volt)
 Binary 1 (signal between 2 and 5 volts)
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Gates are small electronic devices that
compute various functions of these twovalued signals
Friday, October 19, 2007
Computer Architecture I - Class 8
2
Transistor Inverter (NOT
Gate)
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Friday, October 19, 2007
When the input voltage, Vin, is
below a critical value the
transistor turns off and acts
like an infinite resistance, so
Vout is very close to Vcc, an
externally regulated voltage
(typically 5 V)
When Vin exceeds the critical
value the transistor switches
on and acts like a wire,
causing Vout to be pulled down
to ground (0 V)
Computer Architecture I - Class 8
3
NAND Gate
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Friday, October 19, 2007
If both V1 and V2 are
high, both transistors
will conduct and Vout
will be low
If either V1 or V2 is
low the
corresponding
transistor will turn off
and the Vout will be
high
Computer Architecture I - Class 8
4
NOR Gate
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Friday, October 19, 2007
If either V1 or V2 is
high the
corresponding
transistor will turn on
and Vout will be pulled
to ground (0 V)
If both V1 and V2 are
low then Vout will
remain high
Computer Architecture I - Class 8
5
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Gates and Boolean Algebra
Friday, October 19, 2007
Computer Architecture I - Class 8
6
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The Majority Function
Friday, October 19, 2007
Computer Architecture I - Class 8
7
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Boolean Circuits
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Write down the truth table for the function
Provide inverters to generate the complement
(NOT) of each input
Draw an AND gate for each term with a 1 in the
result column
Wire the AND gates to the appropriate inputs
Feed the output of all the AND gates into an OR
gate
Friday, October 19, 2007
Computer Architecture I - Class 8
8
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Boolean Function Notation
Truth table can get too large for more than
3 or 4 inputs
 Use a notation that specifies which
combinations of inputs produce an output
of 1
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 M  A BC  A BC  AB C  ABC
Friday, October 19, 2007
Computer Architecture I - Class 8
9
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Using Only NAND and NOR
Friday, October 19, 2007
Computer Architecture I - Class 8
10
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Circuit Equivalence
Friday, October 19, 2007
Computer Architecture I - Class 8
11
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Boolean Algebra Identities
Friday, October 19, 2007
Computer Architecture I - Class 8
12
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Alternative Symbols for Some
Gates
Friday, October 19, 2007
Computer Architecture I - Class 8
13
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Three Circuits for XOR
Friday, October 19, 2007
Computer Architecture I - Class 8
14
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In-Class Exercise
Use a truth table to show that X = (X AND
Y) OR (X AND NOT Y)
 Show how the AND function can be
constructed from two NAND gates
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Friday, October 19, 2007
Computer Architecture I - Class 8
15
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Integrated Circuits
Friday, October 19, 2007
Computer Architecture I - Class 8
16
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Multiplexer
Friday, October 19, 2007
Computer Architecture I - Class 8
17
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Decoder
Friday, October 19, 2007
Computer Architecture I - Class 8
18
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Comparator
Friday, October 19, 2007
Computer Architecture I - Class 8
19
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Shifter
Friday, October 19, 2007
Computer Architecture I - Class 8
20
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Half Adder
(a)
Friday, October 19, 2007
(b)
Computer Architecture I - Class 8
21
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Full Adder
Friday, October 19, 2007
Computer Architecture I - Class 8
22
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Arithmetic Logic Unit
Friday, October 19, 2007
Computer Architecture I - Class 8
23
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SR Latch
Friday, October 19, 2007
Computer Architecture I - Class 8
24
Clocked SR Latch
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A clocked SR latch.
Friday, October 19, 2007
Computer Architecture I - Class 8
25
Clocked D Latch
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A clocked D latch.
Friday, October 19, 2007
Computer Architecture I - Class 8
26
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Flip-Flops
Friday, October 19, 2007
Computer Architecture I - Class 8
27
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D Flip-Flop
Friday, October 19, 2007
Computer Architecture I - Class 8
28
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Latch and Flip-Flop Symbols
Friday, October 19, 2007
Computer Architecture I - Class 8
29
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Octal Flip-Flop (8-Bit
Register)
Friday, October 19, 2007
Computer Architecture I - Class 8
30
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Memory
Friday, October 19, 2007
Computer Architecture I - Class 8
31
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Buffers
(a) A noninverting buffer.
(b) Effect of (a) when control is high.
(c) Effect of (a) when control is low.
(d) An inverting buffer.
Friday, October 19, 2007
Computer Architecture I - Class 8
32
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4-Mbit Memory Chips
Friday, October 19, 2007
Computer Architecture I - Class 8
33
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CPU Chips
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The logical
pinout of a
generic CPU.
Arrows indicate
input signals and
output signals.
Short diagonal
lines indicate that
multiple pins are
used.
Friday, October 19, 2007
Computer Architecture I - Class 8
34
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Computer Buses
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A bus is a common electrical pathway
between multiple devices
Friday, October 19, 2007
Computer Architecture I - Class 8
35
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Masters and Slaves
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Active devices which can initiate bus transfers
are called masters
Passive devices which wait for requests are
called slaves
Friday, October 19, 2007
Computer Architecture I - Class 8
36
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The Pentium 4
Friday, October 19, 2007
Computer Architecture I - Class 8
37
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The Pentium 4’s Logical
Pinout
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Names in upper
case are the
official Intel
names for
individual signals.
Names in mixed
case are groups
of related signals
or signal
descriptions.
Friday, October 19, 2007
Computer Architecture I - Class 8
38
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Pipelining on the Pentium 4’s
Memory Bus
Friday, October 19, 2007
Computer Architecture I - Class 8
39
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Pentium 4 Bus Structure
Friday, October 19, 2007
Computer Architecture I - Class 8
40
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PCI Bus Arbitration
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The PCI bus uses a centralized bus
arbiter.
Friday, October 19, 2007
Computer Architecture I - Class 8
41
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The Universal Serial Bus
PCI bus is too expensive for low speed
I/O devices (e.g. keyboard, mouse)
 USB was designed by 7 companies as a
better way to attach low speed I/O
devices to a computer
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Friday, October 19, 2007
Computer Architecture I - Class 8
42
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USB Goals
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Users must not have to set switches or jumpers
Users must not have to open the case
Only one kind of cable, for all devices
Devices should get their power from the cable
Up to 127 devices should be attachable to a single
computer
System should support real-time devices
Devices should be installable while the computer is
running
No reboot should be needed after installing a new
device
Devices should be inexpensive to manufacture
Friday, October 19, 2007
Computer Architecture I - Class 8
43