1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. Identify the output expression of the following layout 28. 29. The layout of a static CMOS inverter is given in Figure ( sizes of the NMOS and PMOS transistors (Assuming the layout is done using lambda rules). 30. Consider the following logic function: f (a b)cd Draw the transistor level schematic of this logic function in static CMOS. We are interested in a layout implementation which uses single strip of diffusion in both wells. Construct the Euler path. Derive the layout topology in an n-well process. Draw the stick diagram clearly showing the ordering of the inputs, poly, diffusion (p and n types), the well, and metal lines. 31. Consider the circuit below. a) What is the logic function implemented by CMOS transistor network? Size the NMOS and PMOS devices such that the output resistance is the same as of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. b) What are the input patterns that give the worst case tpHL and tpLH? State the initial input patterns and tell which input(s) has to make a transition to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes. VDD B D C A B A Y C D 32. Design a cascade differential voltage switching logic cell which is described by the equation F ABC D ABCD . Use minimum number of transistors. Consider that normal and inverted values of inputs are available.