WOLAITA SODO UNIVERSITY
COLLEGE OF ENGINEERING
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
COMMUNICATION STREAM
MICROELECTRONIC DIVICE AND CIRCUITS
PROJECT TITLE:
What is the significance of square wave testing in amplifiers?
Prepared by:
YISIHAK KATARO
ENG/R/344/11
DAWIT TASAMA
ENG/R/223/11
January 2022
Wolaita Sodo, Ethiopia
Contents
CHAPTER ONE ................................................................................................................................. 1
SQUARE WAVE TESTING .....................................................Ошибка! Закладка не определена.
Introduction ........................................................................................................................................... 1
Objectives ...................................................................... Ошибка! Закладка не определена.
Significance.......................................................................................................................................... 1
CHAPTER TWO................................................................................................................................ 2
METHODOLOGY............................................................................................................................... 2
2.1Circuit diagrams and Analysis ............................................Ошибка! Закладка не определена.
2.2 Square wave testing of frequency response of amplifiers ........................................................ 3
CHAPTER THREE ........................................................................................................................... 5
MERITS AND DEMERITS ............................................................................................................... 5
3.1 The advantages of square wave testing ....................................................................................... 5
3.2 The disadvantages of square wave testing.................................................................................. 5
3.3 Application ..................................................................................................................................... 6
3.4 Conclusion ...................................................................................................................................... 6
3.5 REFERENCES............................................................................................................................... 7
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CHAPTER ONE
SQUARE WAVE TESTNG
Introduction
Square waves are rich in odd numbered harmonics and have a very simple shape that makes it
easy to observe frequency response limitations in amplifiers. This note discusses how to use
square waves to measure the approximate low and high cut off frequencies of an amplifier.
Amplifiers generally have AC coupled sections that limit the low frequency response and
have shunt capacitances either parasitic or intentional that limit high frequency response. This
not is divided into two sections –one section discusses the measurement of low frequency
response and the other discusses the measurement of high frequency response. In each case
we are looking for the low and high frequencies where the power transfer has dropped to onehalf the mid-band value. These are known as the -3dB frequencies or cut off frequencies.
Objectives
To realize square wave testing of frequency response of amplifiers
1.2 Significance
The significance of this is that the square wave frequency should be greater than ten times
the low frequency cut off.
Testing with square wave input gives a lot more information about the amplifier than
testing with single sine wave signals.
Fig1.N-type network
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CHAPTER TWO
METHODOLOGY
2.1 Working of square wave testing in amplifiers
In dynamic CMOS logic a single clock Φ can be used to accomplish both the pre-charge and
evaluation operations.
When NOR operation we take PMOS in series and NMOS in parallel.
Fig2.schematic
Steps to construct NOR logic circuit
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1. First PMOS is implement in series.
2. NMOS is implement in parallel.
3. Calculate PDN by taking the complement of given Boolean.
4. Finally, calculate the truth table.
Precharge
When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor Mp. During
that time, the evaluate NMOS transistor Me is off, so the pull-down path does not fight the
pull-up path.
Evaluation
When CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned
on. The output is conditionally discharged based on the input values and the pull down
topology. If the inputs are such that the PDN conducts, then a low resistance path exists
between Out and GND and the output is discharged to GND. If the PDN is turned off, the pre
charged value remains stored on the output capacitance CL, During the evaluation phase, the
only possible path between the output node and a supply rail is to GND.
2.2Circuit diagram and analysis
Given a circuit, find out its function. Function may be expressed as
Boolean function & Truth table
3-inputs FET NOR gates
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Fig1. 3-inputs NOR logic gate
Table 1. Truth table analysis
A
B
C
Q1
Q2
Q3
Q4
Q5
Q6
Y
0
0
0
ON
ON
ON
OFF
OFF
OFF
1
0
0
1
ON
ON
OFF
OFF
OFF
ON
0
0
1
0
ON
OFF
ON
OFF
ON
OFF
0
0
1
1
ON
OFF
OFF
OFF
ON
ON
0
1
0
0
OFF
ON
ON
ON
OFF
OFF
0
1
0
1
OFF
ON
OFF
ON
OFF
ON
0
1
1
0
OFF
OFF
ON
ON
ON
OFF
0
1
1
1
OFF
OFF
OFF
ON
ON
ON
0
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CHAPTER THREE
MERITS AND DEMERITS
3.1 The advantages of dynamic CMOS logic
1. They use fewer transistor and therefore, less area. It has only one PMOS.
2. Gates are designed and transistors sized for fast switching characteristics. High performance
circuits use these families.
3. Low power dissipation.
3.2 The disadvantages of dynamic CMOS logic
1. Each gate needs a clock signal that must be routed through the whole circuits. This requires
precise timing control.
2. Clock circuitry runs continuously, drawing significant power.
3. The circuit loses its state if the clock stops.
4. Dynamic circuits more sensitive to noise.
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3.3 Application
CMOS processes were widely implemented and have basically replaced NMOS and bipolar
processes for nearly all digital logic applications. Technology like CMOS is used in different
chips like
 Microcontrollers
 Microprocessors
 SRAM (static RAM) & other digital logic circuits.
3.4 Conclusion
Dynamic logic circuits are usually faster than static counterparts, and require less surface area,
but are more difficult to design, and have higher power dissipation. It use fewer transistor.
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3.5 REFERENCES
[1] Jacob Abraham, ECE Department, University of Texas at Austin October 8, 2020.
[2] M. Annaratone, Digital CMOS Circuit Design, Kluwer, 1986.
[4] Modern VLSI Design – Wayne Wolf, 3 Ed., 1997, Pearson Education.
[3] Published by, www.ijert.org Volume 5, Issue 01.
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