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Lecture 20 ANNOUNCEMENTS • HW#11 is due in 2 weeks, on 11/20. • Review session: Fri. 11/9, 3-5PM in 306 Soda (HP Auditorium) • Midterm #2 (Thursday 11/15 in Sibley Auditorium): • Material of Lectures 11-18 (HW# 7-10; Chapters 6,9,11) • 4 pgs of notes (double-sided, 8.5”×11”), calculator allowed OUTLINE • Review of MOSFET Amplifiers • MOSFET Cascode Stage • MOSFET Current Mirror Reading: Chapter 9 EE105 Fall 2007 Lecture 20, Slide 1 Prof. Liu, UC Berkeley Review: MOSFET Amplifier Design • A MOSFET amplifier circuit should be designed to 1. ensure that the MOSFET operates in the saturation region, 2. allow the desired level of DC current to flow, and 3. couple to a small-signal input source and to an output “load”. Proper “DC biasing” is required! (DC analysis using large-signal MOSFET model) • Key amplifier parameters: (AC analysis using small-signal MOSFET model) – Voltage gain Av vout/vin – Input resistance Rin resistance seen between the input node and ground (with output terminal floating) – Output resistance Rout resistance seen between the output node and ground (with input terminal grounded) EE105 Fall 2007 Lecture 20, Slide 2 Prof. Liu, UC Berkeley MOSFET Models • The large-signal model is used to determine the DC operating point (VGS, VDS, ID) of the MOSFET. • The small-signal model is used to determine how the output responds to an input signal. EE105 Fall 2007 Lecture 20, Slide 3 Prof. Liu, UC Berkeley Comparison of Amplifier Topologies Common Source • Large Av < 0 - degraded by RS • Large Rin Common Gate • Large Av > 0 -degraded by RS • Small Rin - decreased by RS – determined by biasing circuitry • Rout RD • Rout RD • ro decreases Av & Rout but impedance seen looking into the drain can be “boosted” by source degeneration EE105 Fall 2007 • ro decreases Av & Rout but impedance seen looking into the drain can be “boosted” by source degeneration Lecture 20, Slide 4 Source Follower • 0 < Av ≤ 1 • Large Rin – determined by biasing circuitry • Small Rout - decreased by RS • ro decreases Av & Rout Prof. Liu, UC Berkeley Common Source Stage 0 R1 || R2 RD Av RG R1 || R2 1 R S gm Rin R1 || R2 Rout RD EE105 Fall 2007 0 Rout RD rO gm rO RS Lecture 20, Slide 5 Prof. Liu, UC Berkeley Common Gate Stage 0 RS || 1 / g m Av g m RD RS || 1 / g m RG 1 Rin RS gm 0 Rout RD Rout RD rO gm rO RS EE105 Fall 2007 Lecture 20, Slide 6 Prof. Liu, UC Berkeley Source Follower 0 0 Av RS Av 1 RS gm Rin RG Rout 1 rO || RS gm Rin R G 1 || RS gm EE105 Fall 2007 rO || RS Rout Lecture 20, Slide 7 1 || ro || RS gm Prof. Liu, UC Berkeley CS Stage Example 1 • M1 is the amplifying device; M2 and M3 serve as the load. Equivalent circuit for small-signal analysis, showing resistances connected to the drain 1 Av g m1 || rO 3 || rO 2 || rO1 g m3 1 Rout || rO 3 || rO 2 || rO1 g m3 EE105 Fall 2007 Lecture 20, Slide 8 Prof. Liu, UC Berkeley CS Stage Example 2 • M1 is the amplifying device; M3 serves as a source (degeneration) resistance; M2 serves as the load. Equivalent circuit for small-signal analysis 1 0 rO 2 Av 1 1 || rO 3 g m1 g m3 EE105 Fall 2007 Lecture 20, Slide 9 Prof. Liu, UC Berkeley CS Stage vs. CG Stage • With the input signal applied at different locations, these circuits behave differently, although they are identical in other aspects. Common gate amplifier Common source amplifier 1 0 2 0 Av g m1(1 g m2 rO 2 ) RS rO 2 || rO1 EE105 Fall 2007 Lecture 20, Slide 10 Av rO1 1 RS gm2 Prof. Liu, UC Berkeley Composite Stage Example 1 • By replacing M1 and the current source with a Thevenin equivalent circuit, and recognizing the right side as a CG stage, the voltage gain can be easily obtained. 1 0 EE105 Fall 2007 2 0 Av Lecture 20, Slide 11 RD 1 1 g m 2 g m1 Prof. Liu, UC Berkeley Composite Stage Example 2 • This example shows that by probing different nodes in a circuit, different output signals can be obtained. • Vout1 is a result of M1 acting as a source follower, whereas Vout2 is a result of M1 acting as a CS stage with degeneration. 1 || rO 2 vout1 gm2 1 1 vin || rO 2 g m1 g m 2 1 0 vout 2 vin EE105 Fall 2007 Lecture 20, Slide 12 1 || rO 3 || rO 4 g m3 1 1 || rO 2 g m1 g m 2 Prof. Liu, UC Berkeley NMOS Cascode Stage Rout 1 g m1rO1 rO 2 rO1 Rout g m1rO1rO 2 • Unlike a BJT cascode, the output impedance is not limited by . EE105 Fall 2007 Lecture 20, Slide 13 Prof. Liu, UC Berkeley PMOS Cascode Stage Rout 1 g m1rO1 rO 2 rO1 Rout g m1rO1rO 2 EE105 Fall 2007 Lecture 20, Slide 14 Prof. Liu, UC Berkeley Short-Circuit Transconductance • The short-circuit transconductance is a measure of the strength of a circuit in converting an input voltage signal into an output current signal: iout Gm vin • The voltage gain of a linear circuit is vou t 0 Av Gm Rout (Rout is the output resistance of the circuit) EE105 Fall 2007 Lecture 20, Slide 15 Prof. Liu, UC Berkeley Transconductance Example Gm g m1 EE105 Fall 2007 Lecture 20, Slide 16 Prof. Liu, UC Berkeley MOS Cascode Amplifier Av Gm Rout Av g m1 (1 g m 2 rO 2 )rO1 rO 2 Av g m1rO1 g m 2 rO 2 EE105 Fall 2007 Lecture 20, Slide 17 Prof. Liu, UC Berkeley PMOS Cascode Current Source as Load • A large load impedance can be achieved by using a PMOS cascode current source. RoN g m 2 rO 2 rO1 RoP g m 3rO 3 rO 4 Rout RoN || RoP EE105 Fall 2007 Lecture 20, Slide 18 Prof. Liu, UC Berkeley MOS Current Mirror • The motivation behind a current mirror is to duplicate a (scaled version of the) “golden current” to other locations. Current mirror concept Generation of required VGS 1 W 2 I REF nCox VX VTH 2 L REF VX EE105 Fall 2007 2I REF VTH 1 nCox W / L 1 Lecture 20, Slide 19 Current Mirror Circuitry I copy1 1 W nCox VX VTH 2 2 L 1 W / L 1 I copy1 I REF W / L REF Prof. Liu, UC Berkeley MOS Current Mirror – NOT! • This is not a current mirror, because the relationship between VX and IREF is not clearly defined. • The only way to clearly define VX with IREF is to use a diodeconnected MOS since it provides square-law I-V relationship. EE105 Fall 2007 Lecture 20, Slide 20 Prof. Liu, UC Berkeley Example: Current Scaling • MOS current mirrors can be used to scale IREF up or down – I1 = 0.2mA; I2 = 0.5mA 0: EE105 Fall 2007 Lecture 20, Slide 21 Prof. Liu, UC Berkeley Impact of Channel-Length Modulation 0 1 W nCox VX VTH 2 1 VDS1 VD , sat 2 L 1 1 W 2 nCox VX VTH 1 VDS1 VGS VTH 2 L 1 I copy1 1 W 2 I REF nCox VX VTH 1 VGS VD , sat 2 L REF 1 W 2 nCox VX VTH 1 VTH 2 L REF VDS1 VGS 1 VDS1 VGS VTH W / L 1 W / L 1 I copy1 I REF I REF 1 W / LREF W / LREF 1 VTH 1 VTH EE105 Fall 2007 Lecture 20, Slide 22 Prof. Liu, UC Berkeley CMOS Current Mirror EE105 Fall 2007 Lecture 20, Slide 23 Prof. Liu, UC Berkeley