Lecture 14
ANNOUNCEMENTS
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38
• Midterm #1 results (undergrad. scores only):
• N=74; mean=62.8; median=63; std.dev.=8.42
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• The list of misunderstood/forgotten points has been updated.
OUTLINE
• Frequency Response (cont’d)
–
–
–
–
CE stage (final comments)
CB stage
Emitter follower
Cascode stage
Reading: Chapter 11.4-11.6
EE105 Fall 2007
Lecture 14, Slide 1
Prof. Liu, UC Berkeley
25
CE Stage Pole Frequencies, for VA<∞
w p ,in
1

RThev Cin  1  g m RC ro C 
w p ,out 
1


 
1
C 
RC ro  Cout  1 
 


g
R
r
m
C
o

 

Note that wp,out > wp,in
EE105 Fall 2007
Lecture 14, Slide 2
Prof. Liu, UC Berkeley
I/O Impedances of CE Stage
Zin 
1
|| r
jwC  1  g m RC ro C 
EE105 Fall 2007
Z out 
Lecture 14, Slide 3
1
|| RC || ro
jwC  CCS 
Prof. Liu, UC Berkeley
CB Stage: Pole Frequencies
• Note that there is no capacitance between input & output nodes
 No Miller multiplication effect!
CB stage with BJT capacitances shown
w p ,Y
ro  
1

RC CY
CY  C   CCS
w p, X
1

 wT

1 
 RS || C X
gm 

C X  C
EE105 Fall 2007
Lecture 14, Slide 4
Prof. Liu, UC Berkeley
Emitter Follower
• Recall that the emitter follower provides high input impedance
and low output impedance, and is used as a voltage buffer.
Follower stage with BJT capacitances shown
• CL is the load capacitance
EE105 Fall 2007
Circuit for small-signal analysis (Av)
Lecture 14, Slide 5
ro  
Prof. Liu, UC Berkeley
AC Analysis of Emitter Follower
v X  vout  v
• KCL at node X:
vout  v  vin vout  v v
v

 
0
1
1
RS
r
jwC
jwC
v
v
vout
• KCL at output node:  
 g mv 
1
1
r
jwC
jwCL
C
R
1
( jw )
a  S C  C  C  C L  C C L 
gm
vout
gm


C  R C
vin a( jw ) 2  b( jw )  1
b  R C    1  S  L
S
EE105 Fall 2007
Lecture 14, Slide 6

gm


r  g m
Prof. Liu, UC Berkeley
Follower: Zero and Pole Frequencies
vout
vin
C
1
( jw )
gm

a ( jw ) 2  b ( jw )  1
RS
C C  C C L  C C L 
a
gm
b  RS C  
C  RS
 1 
gm 
r
 CL

 gm
• The follower has one zero:
gm
wz 
 2fT
C
• The follower has two poles at lower frequencies:



j
w
j
w
 1 

a ( j w )  b ( jw )  1   1 
 w  w 
p1  
p2 

2
EE105 Fall 2007
Lecture 14, Slide 7
Prof. Liu, UC Berkeley
Emitter Follower: Input Capacitance
• Recall that the voltage gain of an emitter follower is Av 
Follower stage with BJT capacitances shown
ro  
RL
1
RL 
gm
• CXY can be decomposed into
CX and CY at the input and
output nodes, respectively:
C
C X  1  Av C 
1  g m RL

 C
1 
CY  1  C 
g m RL
 Av 
Rin  r    1RL
EE105 Fall 2007
C
Cin  C 
1  g m RL
Lecture 14, Slide 8
Prof. Liu, UC Berkeley
Emitter Follower: Output Impedance
ro  
Circuit for small-signal analysis (Rout)

1

v  i X  g m v  r
jwC

vx  v  ix  g m v RS
Z out



v X RS r C  jw   r  RS r  RS




iX
r C  jw     1
 1
EE105 Fall 2007
Lecture 14, Slide 9
jw
r  RS  / RS r C
jw
1
  1 / r C
1
Prof. Liu, UC Berkeley
Emitter Follower as Active Inductor
Z out
v X RS r C  jw   r  RS r  RS




iX
r C  jw     1
 1
CASE 1: RS < 1/gm
jw
r  RS  / RS r C
jw
1
  1 / r C
1
CASE 2: RS > 1/gm
capacitive behavior
inductive behavior
• A follower is typically used to lower the driving impedance
 RS > 1/gm so that the “active inductor” characteristic on the
right is usually observed.
EE105 Fall 2007
Lecture 14, Slide 10
Prof. Liu, UC Berkeley
Cascode Stage
• Review:
– A CE stage has large Rin but suffers from the Miller effect.
– A CB stage is free from the Miller effect, but has small Rin.
• A cascode stage provides high Rin with minimal Miller effect.
ro  
Av , XY
 1 
vX
  1

  g m1 
vY
 gm2 
 CX  2CXY
EE105 Fall 2007
Lecture 14, Slide 11
Prof. Liu, UC Berkeley
Cascode Stage: Pole Frequencies
Cascode stage with BJT capacitances shown
(Miller approximation applied)
w p, X
ro  
1

RS || r 1 C 1  2C 1 
w p ,Y 
1
1
CCS1  C 2  2C1 
g m2
Note that w p ,Y
w p ,out 
EE105 Fall 2007
Lecture 14, Slide 12
gm2

 2fT 2
C 2
1
RL CCS 2  C  2 
Prof. Liu, UC Berkeley
Cascode Stage: I/O Impedances
ro  
1
Z in  r 1 ||
jw C 1  2C1 
EE105 Fall 2007
Z out  RL ||
Lecture 14, Slide 13
1
jw C 2  CCS 2 
Prof. Liu, UC Berkeley
Summary of Cascode Stage Benefits
• A cascode stage has high output impedance, which is
advantageous for
– achieving high voltage gain
– use as a current source
• In a cascode stage, the Miller effect is reduced, for
improved performance at high frequencies.
EE105 Fall 2007
Lecture 14, Slide 14
Prof. Liu, UC Berkeley