PHGN 435 MOSFET Project Guidelines Spring 2015 Introduction


PHGN 435 MOSFET Project Guidelines

Spring 2015


The goal of this project is for your team to make a

MOSFET (Metal Oxide Semiconductor Field Effect

Transistor) using a predefined mask set.

1 metal gate

A FET is a semiconductor device with three electrical leads. It's essentially back to back pn junctions underneath a metal/oxide layer as shown in Fig. 1. contact p – type source gate oxide

n-type substrate contact p – type drain

In general, current will not flow between the p regions because of the back to back diodes created by the n region in between. The transistor is “off.” When the right bias is applied to the MOS structure, however, the region under the oxide

“inverts” creating a channel of holes in the n-type region (hence the term inversion). At this point



+ ground the p regions are connected by the inverted channel which also contains holes; current can flow, and the transistor is “on” as shown in Fig. 2. o o o o o p – type source p – type drain

There are interesting ways to test this device. If you put a contact on the n-type substrate, from either the source or drain to the substrate you would have a pn-junction and see a diode characteristic. From the gate to the substrate you would have an MOS structure and the C-V curve could tell you the voltage where the channel inverts and MOSFET turns on.

The actual device you are to make is sketched below, and the mask set is in a file on the website in the same folder as this assignment.

Ohmic contact p – type source ~2x10 19 /cm 3 Boron

~1.5um deep metal gate

50nm gate oxide

n-type substrate

Ohmic contact p – type drain ~2x10 19 /cm 3 Boron

~1.5um deep

In the device structure vertical dimensions and dopings don't need to be exact, but should be somewhat close. With diffusion profiles you can't get one exact number. There also could be additional oxide layers present when the device is finished depending upon your process, and this is ok as well as long as the device can be measured and will work. You might have gate oxide, for example, over your source and drain with holes cut in the oxide to allow contacts. You may want to consider a "lift off" technique for the contact metalizations. You haven't done one in class, but it was discussed in your pre-lab assignments. You should build in process check steps to make sure a particular diffusion or oxide growth gave you what it was supposed to give you. You may want to “remove” wafers from the process at key steps along the way so if something goes wrong you don’t have to start at the beginning. The mask set will make several different device sizes.

Each group will get 3 n-type wafers to use as you wish during the process. In addition, there are some ptype wafers available. You also have plenty of silicon pieces from your module work which can be used as “dummy” process characterization pieces.

Process Review: March 17, in-class

In class on March 17, we will do process review presentations. You should plan on presenting your process steps, as well as the tests and characterizations you plan to carry out. In addition to your presentation, you could consider turning in some sort of written documentation.

As you develop your process, keep in mind you have 6-7 class periods to make the transistors and test them. Your procedure should give process steps (e.g. wet oxide growth, spin on photoresist) and conditions (e.g. temperature, spin speed, gas flow rate) supported by your prior measurements, manufacturers data and calculations. It should also (ideally) give a schedule of times; what will be done each week, making sure you don't put two procedures in the same class period that can't be done in that time frame. When I get your procedures next week, I will go over them looking for things that might cause trouble and return them.

To develop your process, you might want to do some looking at books and websites that describe transistor structures to get going. Some of the useful links on the course website such as the SUNY -

Buffalo applets can give you ideas. As your team makes its process, try to play devil's advocate, deciding if some step will do what you want or is likely to eliminate your ability to align on the next step.

Oh, and the first step is to do an RCA clean and grow a wet oxide to act as an anti-diffusion barrier.

MOSFET final reports and presentations

During our finals period, we will have in-class group presentations showing your final process flow and device results. Think about what type of data you might want to collect to tell a compelling story about your work and what you accomplished.

In addition, you will be submitting individual written reports summarizing your results and conclusions.