April 12, 2020 Lev Uvarov
Petersburg Nuclear Physics Institute / University of Florida
Rev 1.0
March 14, 2002
Main FPGA choice is discussed in detail. Table 1 summarizes the chip I/O usage. It also
counts the required number of signal pins for mezzanine card connectors. The appropriate candidates appear to be Virtex II XC2V3000 or bigger devices into FF1152 packages.
The total number of mezzanine card connector pins exceeds the current mezzanine card design by almost 150 and reaches almost 730. It is very unlikely that ALCT and SP could share the same mezzanine card.
Main FPGA of the SP2002 prototype performs reconstruction of complete tracks from individual track segments delivered to it from both Endcup Muon (EMU) CSC chambers over front panel optical links and Front FPGAs and Barrel Drift Tubes (DT) over
Transition board, see Figure 1. Whereas EMU track segments are already aligned in time
into the Front FPGAs, DT track segments still need to be aligned into the Main FPGA.
The CCB and VME interface provides VME access to the Main FPGA chip, as well as delivers timing control signals from the CCB. The DDU interface ensures collecting of
DT track segments and reconstructed tracks into the event frame on the L1A request. The
Main FPGA drives address and control lines of PT LUTs. It also allows loading PT LUTs with data using an additional buffer, which provides a data path to the LUT I/Os.
PT LUT is a 4Mx8 Static RAM (SRAM) implemented either as two Toshiba 4Mx4
TC55V4400FT devices, or as two Toshiba 2Mx8 TC55V8200FT devices with access time of 10-15 ns.
Each bunch crossing the SP2002 sends to the Muon Sorter (MS) 64 bits of data at a
double rate of 80 MHz, organized in two 32-bit frames, Figure 2. LVTTL/GTLP
translators are Fairchild GTLP16617 devices and feature synchronous output enable, allowing clean wired multiplexing on their outputs. Other features include:

Medium drive GTLP capability of 50 mA;

Flow-through pinout;

6.7/8.7ns CLKAB to B-out maximum delay.
In each GTLP16617 transceiver internal triggers sample A-inputs at 80MHz, but only every other sample reaches the transceiver output. Which one succeeds is determined by the CLK40-90 and CLK40-270 signals applied to the /OEAB transceiver enable inputs.
726881302 Page 1 of 6

April 12, 2020 Lev Uvarov
ME2/
ME4
STUBS
ME1
STUBS
9xD24
9xD5
3xD1
6xD24
6xD9
2xD1
DT
STUBS
2xD25
DDU
INT
C2
C8
D16
Main
FPGA
C3
3xD12 + 4xD1
3xA22
3xC4
PT
LUT
D8
3xC1
C1
BUF
C3
CFG
ROM
C2
CCB
&
VME
INT
C10
A8
D16
3xD8
3xD8
3xD8
MUX
Legend:
G – Number of Signal Groups
GxAn – G Groups of n Address Lines
GxCn – G Groups of n Control Lines
CCB & VME INT – Combined CCB and VME Interface
BUF – Buffer
PT LUT – PT Assignment Look Up Table
CFG ROM – Configuration EEPROM
DDU INT – Readout Interface
GxDn– G Groups of n Data Lines ME1 STUBS – ME1 CSC Track Segments
ME2/ME4 STUBS – ME2, ME3, and ME4 CSC Track Segments
DT STUBS – Drift Tube Track Segments
MUX - Multiplexer
Figure 1 Sector Processor Main FPGA Dataflow
Legend:
Ax – x Address Lines
Dx – x Data Lines
Cx – x Control Lines
Main
FPGA
D32
D8
A22
C4
A22
C4
PT
LUT
D8
LVTTL
/GTLP
FRAME2
D32
LVTTL
/GTLP
FRAME1
D32
PT
LUT
D8
A22
C4
PT
LUT
D8
/OEAB=CLK40-90
/OEAB=CLK40-270
CLKAB=CLK80
Figure 2 PT LUT and Multiplexer Details
D32
WIRED
MUX
Back
Plane
726881302 Page 2 of 6

April 12, 2020 Lev Uvarov
Table 1 Main FPGA I/O Count
Virtex-II I/O Pin Count
Signal Name Dir Bits Groups Sum
VME Interface
VM_D
VM_A
/VM_WR
/VM_CE
3.3V
I/O
I
I
I
Subtotal
16
12
1
1
30
1
1
1
1
16
12
1
1
30
ME2-ME4 Muons
CSC_VP
CSC_Q
CSC_PHI
CSC_PHIB
CSC_ETA
CSC _BC1
I
I
I
I
I
I
3.3V or
2.5V
1
4
12
5
7
1
9
9
9
9
9
3
9
36
108
45
63
3
264
Connectors
Pin Count
16
12
1
1
30
Comment
VME Data
VME Subaddress Space [A8:A1]
Write Enable (AL-Active Low)
Chip Select (AL)
9
36
108
45
63
3
264
Valid Pattern
Quality
Phi Azimuthal Angle
Phi Bend Angle
Eta Global Angle
Bunch Crossing One, once per orbit
ME1 Muons
CSC_VP
CSC_Q
CSC_PHI
CSC_PHIB
CSC_ETA
CSC_ID
CSC _BC1
Subtotal 30
I
I
I
I
I
I
I
3.3V or
2.5V
12
5
7
4
1
1
4
DT Muons
DT_Q
DT_PHI
DT_PHIB
DT_BXN
DT_Flag
DT_Synch
DT_CLK40
MS Mux
SP_PHI
SP_ETA
SP_HALO
Subtotal 34
3.3V
I 3
I
Subtotal
I
I
I
I
I
12
5
2
1
1
1
25
3.3V
O 5
O
O
5
1
6
6
6
6
6
6
2
2
2
2
2
2
2
2
3
3
3
6
24
72
30
42
24
2
200
6
24
10
4
2
2
2
50
15
15
3
6
24
72
30
42
24
2
200
6
24
10
4
2
2
2
50
15
15
3
Valid Pattern
Quality
Phi Azimuthal Angle
Phi Bend Angle
Eta Global Angle
CSC ID
Bunch Crossing One, once per orbit
Quality
Phi Azimuthal Angle
Phi Bend Angle
Bunch Crossing
Second Muon Flag
Synchronization / Calibration
Clock40
Phi Azimuthal Angle
Eta Angle
Halo Muon Trigger
726881302 Page 3 of 6

April 12, 2020 Lev Uvarov
Virtex-II I/O Pin Count
Signal Name Dir Bits Groups Sum
SP_CHARGE
SP_BXN
SP_ERROR
SP_SPARE
MX_CLK
O
O
Subtotal
O
O
O
1
2
1
1
3
19
3
1
1
1
1
3
2
1
1
3
43
SP to PT LUT
4M x 8
TC55V4400FT x 2
PT_DPHI
PT_SIGN
PT_ETA
3.3V
O 13
O
O
1
4
PT_MODE
/PT_CE
O
O
/PT_WE
/PT_OE
Buffer (for PT LUT loading)
BUF_D
O
O
Subtotal
3.3V
O 8
4
1
1
2
26
/BUF_OE
/BUF_DIR
O
O
1
1
Subtotal
DDU Readout 3.3V
DDU_D
DDU_VP
DDU_RR
DDU_RA
O 16
O
I
O
1
1
1
DDU_ST
DDU_RSVD
I 1
I/O 3
Fast Control
Subtotal 23
3.3V
CCB_CLK40
CCB_CLKEN
CCB_BC0
CCB_BCR
I
I
I
I
1
1
1
1
CCB_TEST
CCB_L1A
CCB_SPARE
I
I
I
Subtotal
Fast Monitoring 3.3V
8
FM_OSY
FM_SPARE
O
O
1
1
1
1
2
Configuration
Subtotal
3.3V
2
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
3
1
12
3
3
6
78
39
3
12
8
1
1
2
1
1
2
1
1
1
1
1
3
26
16
4
1
1
8
3
1
12
Connectors
Pin Count
3
2
1
Muon Sign
Comment
2 LSB of BXN
Error
1
3
Spare
Mux Clocks
43
39
3
12
12
3
3
6
78
8
3
1
12
16
4
1
1
1
3
26
1
1
1
1
1
1
2
8
1
1
2
Delta Phi Azimuthal Angle
Sign
Eta Angle
Mode
Chip Enable (AL)
Write Enable (AL)
Output Enable (AL)
Data
Chip Enable (AL)
Output Enable (AL)
Readout Data
Valid Pattern
Readout Request
Request Acknowledge
Readout Start
Readout Reserved
Main Clock
Clock Enable
Bunch Counter Zero
Bunch Counter Reset
Test Request
L1 Accept
Reserved
Out of Synch
Reserved
726881302 Page 4 of 6

April 12, 2020 Lev Uvarov
Signal Name
CFG_M
CFG_DIN
CFG_DOUT
CFG_INIT
CFG_CCLK
Virtex-II I/O Pin Count
Dir Bits Groups Sum
I 3 1
I
O
1
1
1
1
1
1
I/O 1
I 1
CFG_PROG_B
CFG_DONE
I 1
I/O 1
Subtotal 9
3.3V JTAG Modes
CFG_TMS
CFG_TDO
I
O
1
1
CFG_TDI
CFG_TCK
I 1
1 I
Subtotal
1
1
1
1
1
1
1
1
1
3
0
Connectors
Pin Count
3
1
1
Configuration Mode Bits
Serial Input
Comment
Serial Output
1
1
Delay Configuration
Configuration Clock
1
1
Hard Reset from CCB
Completion of Configuration
9
1
1
Test Mode Select
Test Data Out
1
1
4
Test Data In
Test Clock
TOTAL 716 726 XC2V3000-5FF1152C or bigger
The total number of required I/Os for Main SP2002 FPGA reaches 716.
Ошибка!
Неверная ссылка закладки.
gives us available number of user I/Os for each device/package combination of the Virtex-II FPGA series. The applicable candidates are devices in FF1152 package (highlighted in light green).
Table 2 Virtex-II Device/Package Combinations and Maximum Number of Available I/Os
Package
CS144
FG256
FG456
FG676
FF896
FF1152
FF1517
BG575
BG728
BF957
XC2V
40
88
88
XC2V
80
92
120
XC2V
250
92
172
200
XC2V
500
172
264
Virtex-II Available I/Os
XC2V
1000
XC2V
1500
XC2V
2000
172
324
432
328
392
528
392
456
624
408
456
624
XC2V
3000
484
720
516
684
XC2V
4000
824
XC2V
6000
824
912 1104 1108
684 684 684
XC2V
8000
824
The smallest XC2V3000 device provides as many as 720 user I/Os, whereas XC2V4000 and bigger devices – 824 I/Os. The preliminary number of required user I/Os is very close to 720, and using the smallest device may become an obstacle for development as design progresses and request for more I/Os emerges.
726881302 Page 5 of 6

April 12, 2020 Lev Uvarov
It is assumed that the Main FPGA chip is located on the mezzanine card, square in shape, which is stacked to the main board using 4 Samtec FOLC/MOLC connectors. The
FOLC/MOLC interconnect system features 4-row of 2 mm pitch contacts, and up to 50 contacts per row. 200 contacts per connector, or 800 contacts in total give enough flexibility for SP2002 board routing.
Table 3 Revision Histories
Date Revision #
February 26, 2002 Initial Proposal
What’s new
March 14, 2002 Rev 1.0
Figure 1 completely updated. EMU Muon box has been split into
two boxes for ME2/ME4 and ME1 track segments respectively.
726881302 Page 6 of 6