Status of the Level-1 CSC
Track-Finder
D.Acosta, A.Madorsky, B.Scurlock, S.M.Wang
University of Florida
A.Atamanchuk, V.Golovtsov, B.Razmyslovich
St. Petersburg Nuclear Physics Institute
Level-1 Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver Sector Processor
OPTICAL
FE
TMB
PC
2P / chamber
3P / port card
SR
SP
LCT
FE
Wire FE cards
3P / sector
Wire LCT card
36µ
In counting house
CSC Muon Sorter
On chamber
On periphery
RPC DT
4P
4P
Global P Trigger
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
4P
4P
Global L1
2
Rapidity Coverage of CSC
Track Finder
•
•
•
•
Require a track stub in ME2 or ME3 for endcap
Require a stub in ME2 for overlap region
Limits rapidity coverage to η > 1
Allows CSC and DT processing on one board
η = 0.5
η = 1.1 η = 1
MB/1/4
MB/2/4
ME/1/3
YB/0/3
MB/1/3
MB/0/3
YB/2/2
YB/1/2
YB/0/2
MB/2/2
YB/2/1
MB/1/2
YB/1/1
MB/0/2
YB/0/1
MB/2/1
MB/1/1
MB/0/1
ME/1/2
YE/2
5.975 m
4.905 m
4.020 m
2.950 m 2.864 m
2.700 m
HB/1
1.9415 m
HE/1
1.711 m
HF/1
1.811 m
EB/1
EE/1
YE/1
3.800 m
CB/0
ME/1/1
ME/2/1
η = 3.0
MB/2/3
ME/2/2
ME/3/2
ME/3/1
ME/4/1
η = 2.4
YE/3
10.86 m
ME/4/2
η = 1.479
YB/1/3
YB/2/3
7.380 m
7.000 m
MB/0/4
1.290 m 1.185 m
SB/1
0.440 m
η = 5.31
0.00 m
0.000 m
2.935 m
3.90 m
4.332 m
5.68 m
6.66 m
6.45 m
7.24 m
8.495 m
9.75 m
10.83 m
10.63 m
10.91 m
14.53 m
14.96 m
14.56 m
SE/1
CMS - PARA- 003 - 14/10/97
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
3
PP
/pg/hr
Track-Finder Architecture
• Track-Finder implemented as 12 Sector Processors
• Each Sector Processor:
– Implemented on a 9U VME card
– Processes 15 CSC segments and 8 DT segments
– Identifies ≤ 3 muons per 60°
• CSC data received by 3 Sector Receiver cards
–
–
–
–
Each receives 6 track segments on optical links
Reformats data to ϕ, ϕb , η
Applies alignment corrections
Communicates to Sector Processors via custom
point-to-point backplane
– Presently under development at UCLA
• DT data sent to transition board at back of crate
• Custom point-to-point backplane:
– Delivers ~600 bits every 25 ns (3 GB/s)
– Operates at 280 MHz to reduce connections:
• National Channel Link 28:4 serialization
– Presently being prototyped in Florida
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
4
Track-Finder Backplane
Bottom Top
rows
rows
a,b
d,e
Bottom Top
rows
rows
a,b
d,e
Bottom Top
rows
rows
a,b
d,e
Bottom Top
rows
rows
a,b
,e
To Barrel
From Barrel
To Barrel
To Barrel
DS90LV031A(transmitter) and DS90LV032A(receiver)
DS90CR285(transmitter) and DS90CR286(receiver)
DS90CR217(transmitter)
D. Acosta, University of Florida
DS90CR218(receiver)
TriDAS Review, November 8, 1999
5
Sector Processor Layout
Custom
Backplane
P1
Control
Logic
CCB
SR
4 st.
Channel Links
Global Buffer (FIFOs)
Extrapolation Units
TAU2
(endcap)
VME
Interface
2 Bunch Crossing Analyzer
FPGA
Download
Logic
Final
Selection
Unit
TAU1
(overlap)
Pt-assignment
Units(LUTs)
Channel Links
Output
Data
Storage
Pt-assignment Units (FPGAs)
LED
Drivers
Control Logic
(Clock distribution, SRAM read/write
and other devices)
Transition
Module
SR
1,3 st.
SR
1,2 st.
SR
Barrel
Latency expected to be 14 B.X.
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
6
Sector Processor Logic
• Latch input and hold for possibly more than one B.X.
– Allows for timing errors from trigger primitives
• Perform all possible station-to-station extrapolations
in parallel
– Simultaneously search roads in ϕ and η
• Assemble 3- and 4-station tracks from 2-station
extrapolations
• Cancel redundant short tracks if track is 3 or 4
stations in length
• Select the three best candidates
• Calculate PT , ϕ, η and send to CSC muon sorter
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
7
Two Bunch Crossing Mode
• Input data can be latched for 2 B.X. to accommodate
timing errors from trigger primitives
• Sector Processor still reports trigger at correct B.X.
• Assume earliest stub defines correct B.X.
• Select stubs from later B.X. only if Track-Finder input
is not full (i.e. keep input count the same)
• Cancel double triggers
ME4
ME3
ME2
ME1
N–1
N
N–1
N+1
N
Double count
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
8
Assignment Unit
• Determines ϕ, η, PT, and quality of the selected 3
best muons. (PT and quality ⇒ Rank)
• PT assignment uses ϕ, η measurements from 2 or 3
stations
– δPT/PT ~ 30% with only 2 stations
– δPT/PT ~ 20% with 3 stations ⇒ improves Level-1 rate
reduction
• Implemented with FPGA preprocessing followed by
large SRAM look-up table
2Mb×8 SRAM
FPGA
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
9
σ( 1/Ptrec - 1/Ptgen )/( 1/Ptgen )
PT Resolution
0.7
Pt = 5 GeV (2 Stn)
(ME1-ME2)
0.6
0.5
ME1/3
MB1
Pt = 5 GeV (3 Stn)
(ME1-ME2-ME3)
ME1/2
ME1/1
0.4
0.3
0.2
0.1
0
0.8
1
1.2
D. Acosta, University of Florida
1.4
1.6
1.8
TriDAS Review, November 8, 1999
2
2.2
2.4
ηrec
10
Trigger Rate
Rate dN/dηdt (kHz)
Single µ Rate (Min Bias sample)
10
4
10 3
2 Stn Pt (|η| > 1.2)
3 Stn Pt (|η| > 1.2)
10 2
10
1
10
10
-1
-2
34
-2 -1
L = 10 cm s
10
-3
1
10
10
2
Ptmin (GeV)
3-station measurement provides a large safety factor in
reducing the single µ rate below 1 kHz / unit rapidity
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
11
Track-Finder Output
• 5-bit PT and 2-bit Quality are combined into a 7-bit
Rank
• This rank is used by the CSC Muon Sorter
• Output of Muon Sorter can be the rank, or PT and
Quality via LUT
• Depends on how CSC and DT muons will be
combined and ranked by the Global Muon Trigger
From Sector Processor to Muon Sorter:
Variable Precision
M
2.5q
0.075
K
Rank
PT & Quality
Sign
–
BXN
–
Error
–
Total
Range
0–60q
0.9–2.4
2–140 GeV
–
–
–
Bits / P
5
5
5+2
1
–
–
18
Bits / 3P
15
15
21
3
4
1
59
Add 3 bits to ϕ and 1 bit to η for Muon Sorter to
Global Muon Trigger
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
12
Sector Processor Design Status
• Conceptual design complete
– Documented in CMS Note (and eventually TDR)
• Schematics about 80% complete
• FPGA design about 50% complete
• PCB layout started
• Backplane design started
– Tests underway at Florida
• Test adapter design about 50% complete
– Will provide simulated DT signals as well as CSC
• Test software started, but much work to do:
– Downloading FPGA/RAM configuration
– Downloading patterns
– Verification
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
13
Prototype Schedule
• February 2000
– Finish schematics
– Finish FPGA design
– Finalize Sector Receiver/Sector Processor interface
• March 2000
– Finish board layout
– Begin construction
• May 2000
– Begin testing of Sector Processor only
• June 2000
– Begin trigger crate tests with backplane, Sector
Receiver, and Sector Processor
• October 2000
– Finish all tests
• November 2000
– Finish TDR!
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
14
Summary of CSC Track-Finder
• Conceptual design complete
• 12 Sector Processors cover CSC and CSC/DT
overlap
– 1.0 < η < 2.4 and ∆φ = 60° on one board
• Track-finding algorithms are three-dimensional
– Improves background suppression
• PT assignment includes φ,η measurements from 3
stations
– δPT/PT ~ 20%
(30% with only 2 stations)
– Significantly improves rate reduction at Level-1
• Inputs can be latched for 2 B.X.
– Tolerates timing errors from trigger primitives
•
•
•
•
Latency expected to be only 14 B.X.
Fully re-programmable
Xilinx Virtex FPGAs and SRAM used
Board layout and backplane design started
D. Acosta, University of Florida
TriDAS Review, November 8, 1999
15