CSC Trigger Electronics in
the Counting Room
Darin Acosta
University of Florida
TriDAS Review
May 19, 1999
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
1
Outline
Overview
Sector Receiver functionality
Sector Processor functionality
Muon Sorter functionality
Crate design
Progress
Plans
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
2
CSC Muon Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver Sector Processor
OPTICAL
FE
SR
TMB
PC
2µ / chamber
3µ / port card
SP
LCT
FE
Wire FE cards
3µ / sector
Wire LCT card
In counting house
CSC Muon Sorter
RPC
On chamber
On periphery
4µ
DT
4µ
4µ
Global µ Trigger
Global L1
4µ
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
3
Muon Track-Finding
Perform 3D track-finding from trigger primitives
Measure PT, ϕ, and η
Transmit highest PT candidates to Global L1
θ
ϕ
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
4
CSC Track-Finder
Requirements
High efficiency
Trigger Rate:
• Single muon rate < few kHz at L = 1034cm-2 s-1
Resolution:
• σPt / Pt ≤ 30%
(Requires η information)
Multi-muon capability:
• ≤ 3 muons per 60° sector
• Best 4 muons sent to Global L1
Redundancy
• Require only 2 stations out of 3 (or 4)
Minimal latency, programmable
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
5
Muon Rate dN/dηdt (Hz)
CSC Muon Trigger Rates
10 7
10
34
• Single µ rate from
Pythia, convoluted
with efficiency curve
-2 -1
L = 10 cm s
6
10 5
50%
10 4
40%
10 3
10 2
30%
• Require rates < 1 kHz
per unit rapidity
10
1
10
10
• Thresholds set for
90% efficiency
20%
CSC resolution from CMSIM
-1
10% resolution
-2
PYTHIA6
1
10
10
2
Effective PT Threshold (GeV/c)
D. Acosta, University of Florida
• Not satisfied for PT
resolution worse than
30%
TriDAS Review: May 19, 1999
6
Trigger Regions in η
Overlap
1.2 > η > 0.9
Separate
trigger
regions
DT
η = 0.5
η = 1.1 η = 1
MB/1/4
MB/2/4
YB/1/3
YB/2/3
ME/1/3
ME/2/2
MB/2/3
MB/1/3
MB/0/3
YB/1/2
YB/0/2
MB/2/2
YB/2/1
MB/1/2
YB/1/1
MB/0/2
YB/0/1
MB/2/1
MB/1/1
MB/0/1
ME/1/2
7.380 m
7.000 m
MB4
5.975 m
MB3
4.905 m
MB2
YB/0/3
YB/2/2
4.020 m
3.800 m
MB1
CB/0
2.950 m 2.864 m
2.700 m
ME/1/1
YE/1
HB/1
1.9415 m
HE/1
1.711 m
HF/1
1.811 m
EB/1
EE/1
η = 3.0
ME/2/1
ME/3/1
ME/4/1
4
YE/2
η = 2.
YE/3
10.86 m
CSC
ME/3/2
ME/4/2
η = 1.479
MB/0/4
1.290 m 1.185 m
SB/1
0.440 m
η = 5.31
0.00 m
ME3 ME2
D. Acosta, University of Florida
ME1
TriDAS Review: May 19, 1999
0.000 m
2.935 m
3.90 m
4.332 m
5.68 m
6.66 m
6.45 m
7.24 m
8.495 m
9.75 m
10.83 m
10.63 m
10.91 m
14.53 m
14.96 m
14.56 m
SE/1
CMS - PARA- 003 - 14/10/97
PP
/pg/hr
7
Trigger Regions in ϕ
ME1/3
Track-Finding
performed in
independent
60° sectors
MB2/2
MB2/1
Illustration of
overlap region
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
8
Overlap Region Issues
• CSC and DT segments are required for efficient
coverage of 0.9 < |η| < 1.2
• Agreement with Vienna and Bologna on
Barrel/Endcap boundary (CMS IN 1999/015)
⇒ Barrel and Endcap Track-Finders are
fundamentally different (2D vs. 3D)
⇒ Information sent both ways
• MB2/1+MB2/2 ⇒ CSC T-F
ME1/3+ME2/2 ⇒ DT T-F
⇒ Programmable sharp η boundary
• Avoids duplication of single muon in overlap region
⇒ Separate sorting of CSC and DT muons
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
9
Sector Partitioning
20°
20°
20°
Sector Sector Sector
30° or 20°
subsectors in
ME1
ME1 Left
ME1/3
10°
10° 10° 10° 10° 10°
ME1/2
10° 10° 10° 10° 10° 10°
ME1/1
ME1/A
10° 10° 10° 10° 10° 10°
60° Sector
ME2/2 10°
10° 10° 10° 10° 10°
ME2/1
20°
20°
20°
ME3/2
10°
10° 10° 10° 10° 10°
60° sectors in
ME2 —ME4
ME3/1
20°
20°
20°
10° 10°10°10° 10°10°
16µ
2 or 3 MPC
60° Sector
ME1 Center ME1 Right
Muon
Port
Card
16µ
Muon
Port
Card
2µ
6 µ / SR
2µ
Sector
Receiver
Barrel
18µ
16µ
Muon
Port
Card
18µ
Muon
Port
Card
Muon
Port
Card
2µ
3µ
6µ
CSC
Sector
Processor
6µ
3µ
Sector
Receiver
OVR
Sector
Processor
Barrel
Barrel
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
10
Sector Receiver Functionality
UCLA
• Receives 6 µ segments via 12 optical links
from 2 Muon Port Cards
• Synchronizes the data
• Reformats the data
⇒LCT bit pattern → η, ϕ, Ψ, ...
via LUT
• Applies alignment corrections
• Communicates to Sector Processors via
custom backplane (Channel Link)
• Fans out signals to DT Track-Finder
}
• Functional block diagram developed and
board layout started
⇒
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
11
Required Precision of Data
Azimuthal angle ϕ:
• 12 bits / 60° ⇒ 1 bit / 0.26 mrad (0.1 strip)
Bend angle Ψ:
Ψ
• 6 bits / ±45° ⇒ 1 bit / 60 mrad
ϕ2
ϕ1
Polar angle η:
• 6 bits / 1.5 units ⇒ 1 bit / 0.025
∆ϕ
Quality:
• 3 bits
Chamber i.d.:
• 6 bits
Accelerator µ flag: 1 bit
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
34 bits per CSC
segment to Sector
Processor
12
Sector Receiver Board
Layout
SRAM LUTs
muon 1
VME
Optical
Receivers
muon 2
muon 3
optical fiber
muon 4
muon 5
muon 6
Channel Link transmitters & connectors
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
13
Sector Processor
Functionality
Florida
• Identify and measure muons from ~ 600 bits
every 25ns (3 GB/s)
• Perform all possible station-to-station
extrapolations in parallel
⇒ Simultaneously search roads in ϕ and η
• Assemble 3- and 4-station tracks from 2-station
extrapolations
• Cancel redundant short tracks if track is 3 or 4
stations in length
• Select the three best candidates
• Calculate PT, ϕ, η and send to CSC muon sorter:
22 bits × 3 = 66 bits
• Functional block diagram developed
⇒
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
14
Sector Processor Block
Diagram
Extrapolation Units
4 (3x26)
3 (3x26)
Final Selection Unit
EU4
2-4
2–4
(18 bits)
3-4
3-2
TAU 2
3-1
2(3x26)
2–3
(18 bits)
2-1
3 (3x26)
EU2
1-3
Track 3
Track 2
Track 1
2 (3x26)
EU1
1-2
1–2
(36 bits)
Assignment Unit
Data
Extraction
MUX
D. Acosta, University of Florida
LID
Pt
LUT
Output
Data
3x22=66
TriDAS Review: May 19, 1999
OUTPUT
CONNECTOR
1(6x26)
CLOCKED
FIFO
U – Extrapolation Unit
AU – Track Assembling Unit
SU – Final Selection Unit
TA –Selected Track Address
ID – Look-Up Input Data
1(6x26)
1– 3
(36 bits)
TAU 1
STA
- Downloading/
Readout Line
Track 4
2-4
2-3
- Control Line
FSU
Track 5
3 (3x26)
EU3
2-3
Track 6
VME BUS
2 (3x26)
DOWNLOADING/
READOUT
INTERFACE
- Data Line
Track Assemblers
8x3
Control
EU5
3 -4
4 (3x26)
Input Data
15x34=510
Data
INPUT DATA &
CONTROL
INTERFACE
9U CUSTOM
BACKPLANE
Input
3–4
(9 Extrapolations or
18 bits)
15
Sector Processor Logic
Chamber
ME4
41
42
43
Chamber
ME3
31
32
33
Chamber
ME2
21
22
23
Chamber
ME1
1
1*
*
1
1
*
2
1
*
3
1
**
1**
D. Acosta, University of Florida
**
1 1 2
1**3
• Perform all
combinations of
extrapolations in
parallel:
1i ↔ 2k , 1i ↔ 3k, 2i ↔3k
2i ↔ 4k , 3i ↔ 4k
But not 1i ↔ 4k
• Track Assembler takes
best 2 or 3
extrapolations per
reference segment
TriDAS Review: May 19, 1999
16
Extrapolation Unit Detail
η1
5
η2
5
η1−η2
6
LUT
SM
& Match η
64x1
η1
5
η road finder
η1−η2
LUT
LUT
32x6
32x1
η2
5
LUT
LUT
32x6
32x2
Input Data
42 Bits
η1
η2
5
5
φ1
7
φ2
ψ1
SL
MUX
2x1
5
8
7
SM
φ1−φ2
6
LUT
LUT
32x6
6
6
6
6
LUT
6
CMP
η∗, ∆φ
6
CMP
η∗∗, ∆φ
6
CMP
η∗∗∗, ∆φ
3
LUT
6
6
6
64x6
Q1 3
Q2 3
6
PRE
LUT
16x2
2
3-2
Match φ
2
Output Data
2
&
q1,q2
Result quality
Coarse PT assign
&
8x1
6
ψ2
z
SM
7
∆φ−ψ1
SM
7
∆φ−ψ2
LUT
Match ψ1
128x1
LUT
Match ψ2
ϕ road finder
128x1
ϕ
2
64x2
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
17
Data Stream Paths
33
2 best
2 – 33
1 – 3, 2 – 3, 3 – 4
Extrapolations
3 best
1 – 33
2 best
32 – 4
32
2 best
2 – 32
2 best
33 – 4
3 best
1 – 32
Track Assembler
Unit (TAU2)
Stream 2
Track types:
1–3
2–3
3–4
1–3–4
2–3–4
2 best
31 – 4
31
2 best
2 – 31
3 best
1 – 31
Extrapolation
Units
2 best
21 – 4
2 best
21 – 3
Track Assembler
Unit (TAU1)
3 best
1 – 21
21
Track types:
1–2
2–4
1–2–3
1–2–4
1–2–3–4
Stream 1
2 best
2 2– 4
1 – 2, 2 – 3, 2 – 4
Extrapolations
2 best
22 – 3
22
3 best
1 – 22
2 best
23 – 4
2 best
23 – 3
23
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
3 best
1 – 23
18
Track Assembler Unit (TAU1)
15 ([2bits Quality + 3bits Number] x 3)
6
6
12
6
6
3 best
extrapolations
4 (2+2) best
extrapolations
3 best
extrapolations
4(2+2) best
extrapolations
15
9
3bits + 3bits + 3bits
according to the order of
priority (PCB Layout)
8
4
8
9
4
2bits + 2bits
according to the order of
priority (PCB Layout)
15
9
9
8
4
8
4
9
Multiplexer
4
12
6
6
3 best
extrapolations
4(2+2) best
extrapolations
15
9
8
4
8
4
4
Sel1
Sel2
Sel3
4
4⇒5
4⇒5
4⇒5
5
5
5
36
6
4
21 – 1
21 – 3
21 – 4
6
4
4
4
LUT
32Kx16
Link
21
6
4
4
Link
22
6
4
4
Extrapolations Quality
D. Acosta, University of Florida
Link
23
4
A3
4
A2
4
A1
4
B3
4
B2
4
B1
4
C3
4
C2
4
C1
4
Selection
Unit
To Final Selection Unit
(Extrapolation Quality Part)
8 ([2bits Quality + 2bits Number] x 2)
12
To Final Selection Unit
(Hit Number Part)
7 bits:
Hit number (1st chamber) – 3 b
Hit number (2nd chamber) – 2
Hit number (3rd chamber) – 2 b
Hit number (4th chamber) – 2 b
Track Absolute Quality
4
4
(3 Best
Tracks)
2bits + 2bits:
2 bits select 21, 22 or 23 stream
2bits select h., m. or l. priority track.
Track Local Quality
TriDAS Review: May 19, 1999
19
9
Track 5
9
Track 4
9
(if we need only 2 track segments
for Pt calculation)
8
Track 3
9
Track 2
9
Track 1
9
8
Sel1 Sel2 Sel3
We should compare:
Track1-Track4; Track1-Track5;
Track1-Track6; Track2-Track4;
Track2-Track5; Track2-Track6;
Track3-Track4; Track3-Track5;
Track3-Track6 (9 bits as total)
10
10
10
9
9
9
9
Track 6
Track 5
Track 4
Track 3
Track 2
Track 1
D. Acosta, University of Florida
5
5
5
5
5
5
Extrapolations
Quality Comparators
(9 Units)
9
Hit Number
Comparators
(9 Units)
9
9
Final
Decision
Unit
To Data Extraction Multiplexer
Stream 2
Track 6
8 bits:
1st track segment number – 4 bits;
2nd track segment number – 4 bits.
MUX
8
Stream 1
From Track Assemling Unit
(Hit Number Part)
Final Selection Unit
Each track consists of 4 track
segments as maximum
⇓
6 Tracks has 24 track
segments
⇓
We need 10 (5+5)bits to
describe all possible
combinations
LUT
256Kx32
9
TriDAS Review: May 19, 1999
20
Muon Sorter Functionality
• The 3 highest rank muons from each Sector
Processor are sent to the CSC muon sorter,
which selects the 4 highest rank
• Total muon count:
Rice
⇒ 3 muons × 6 sectors × 2 endcaps × 2 regions = 72
muons for CSC and OVL regions
• Sort is based on 7 bits (5 bits for PT and 2 bits
for quality)
⇒ Basic sorting unit design (4 best out of 8) is complete
• Input: 72 × 22 bits = 1584 bits
• Output: 4 × 22 bits = 88 bits
⇒ Sent to Global L1 Muon Trigger for association with RPC
and DT triggers
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
21
Muon Sorter Block Diagram
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
22
CSC Track-Finder Crate
Organization
Endcap 1
360°
CSC+OVL
Endcap 2
CSC+OVL
CSC and overlap regions
handled in same crate
240°
120°
ϕ
Two 60° sectors
per crate
0°
CSC Counting House electronics:
Racks: 3 or 4
Crates: 6
Sector Receivers: 24
Sector Processors: 24
Muon Sorter: 1
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
23
Layout for Track-Finder
Crate
Two 60° sectors housed in one 9U
VME crate with custom backplane
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
24
Backplane Connections
• Channel Link
custom
backplane
• AMP Z-Pack
2mm connectors
208 bits
104 bits
D. Acosta, University of Florida
208 bits
Not shown: 204 bits (8 µ)
from DT trigger to SP-OVR
TriDAS Review: May 19, 1999
25
Design Progress
• Full conceptual design from trigger primitives
to Global L1 Trigger
⇒ Bit counts fully documented
⇒ Crate design underway
⇒ Sector Receiver functionality defined
⇒ Sector Processor algorithms defined
⇒ Sort algorithms defined
• Simulation of Track-Finder performance
underway
⇒ resolution, efficiency, rate, chamber
misalignment
• Prototyping started
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
26
Milestones / Schedule
√ D387 – 1999 Mar, Sector Receiver Initial System Design (UCLA)
√ D331 – 1999 Mar, Sector Processor Initial System Design (Florida)
D390 – 1999 Sep, Sector Receiver Prototype Design (UCLA)
D332 – 1999 Sep, Sector Processor Prototype Design (Florida)
on schedule
D391 – 2000 Jan, Sector Receiver Prototype (UCLA)
D334 – 2000 Jan, Sector Processor Prototype (Florida)
D335 – 2000 Apr, Sector Receiver / Processor Crate Test
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
27
Documentation
• Sector Processor design and simulation:
• http://www.phys.ufl.edu/~acosta/cms/trigger.html
• Sector Receiver design and overall CSC
trigger bit document:
• http://www-collider.physics.ucla.edu/cms/trigger/
D. Acosta, University of Florida
TriDAS Review: May 19, 1999
28