Status of CSC Trigger
Darin Acosta
University of Florida
ALCT Boards (EMU subsystem)
Status:
UCLA
284 boards produced
Î 153 tested and passed
Î 101 shipped out
Î
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
TMB in Preproduction
UCLA
Status:
18 built
Î Firmware being
updated
Î
Main FPGA
(on back)
XILINX XCV1000E
Input
connectors
Mezzanine board
From 5 CFEB’s
Input
connectors
From ALCT
9Generates Cathode LCT trigger with input from CFEB (comparator)
9Matches ALCT and CLCT; sends trigger primitive info via MPC to
Lev-1 muon trigger, sends anode and cathode hits to DMB.
CMS Week, 3 Dec 2002
3
D.Acosta, University of Florida
Muon Port Card
Rice
VME
Interface
(glue logic)
GTLP
Receivers
Optomodules
CMS Week, 3 Dec 2002
TLK2501
serializers
Mezzanine card
4
D.Acosta, University of Florida
MPC Design Status
Rice
• 3 boards have been fabricated and assembled in summer
• Have 6 UCLA mezzanine cards in hand
• Tested MPC standalone (sorter logic) and with one and
two Trigger Motherboards and full-size custom backplane
- various patterns sent from TMB to MPC at 80Mhz
- feedback “winner” bits from MPC to TMB
- periodic FPGA reconfiguration from EPROMs (both
MPC and TMB) upon “hard reset”
- measured the board latency
Waiting to test with Sector Receiver/Processor
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
Muon Sorter
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
MS
CCB
Clock and Control
Board
SBS 620 Controller
CSC Track-Finder Crate Design
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
Sector Processor)
(60° sector)
From MPC
(chamber 4)
From MPC
(chamber 3)
From MPC
(chamber 2)
From Trigger
Timing &
Control
From MPC
(chamber 1B)
From MPC
(chamber 1A)
To
Global Trigger
•
To DAQ
Single Track-Finder Crate Design with 1.6 Gbit/s optical links
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
CSC Track-Finder GTLP Backplane
DDU
MPCs
Endcap 1 (6 SPs) CCB Sorter Endcap 2 (6 SPs)
(for DAQ) (for test)
Connections to
DT Transition
cards
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
CSC Sector Processor (2nd Prototype)
Florida
Phi Global LUT
Eta Global LUT
Phi Local LUT
DC-DC Converter
EEPROM
Stiffener
Indicators
FM RJ45
Fits all of previous
SP board logic!
VME/CCB
FPGA
TLK2501
Transceiver
From CCB
Front FPGA
To MS
DDU FPGA
PT LUT
Main
FPGA
Mezzanine
Card
Optical
Transceivers
(16)
MB1-to-SP
ME1-to-DT
SRAM
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
Sector Processor Status
Schematics complete
Mezzanine card layout complete
Main board:
Florida
Problems encountered using OrCAD Layout
‡ Board is too complex, manual routing is labor intensive,
and program pushed to its limits
‡ Suffered catastrophic failure
Î Sent routing to outside vendor for completion
(they use Cadence Allegro for layout)
‡ Preliminary layout received
‡ Under review by design engineers
Î Fabrication and Assembly expected to take 3 weeks
‡ Prototype ready by January
Î
Components ordered, most in hand
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
SP Firmware Development
1.
VME/CCB interface and Front FPGAs
Î
2.
PNPI. Started. Necessary for optical link tests to MPCs
SP chip
Î
3.
Florida
Trigger logic done, but supporting logic still to do
DDU (DAQ interface) firmware
Î
PNPI. Still to be done. Not critical for initial tests.
Hope to have first two items ready when board
fabrication is complete
Î
Approximately Jan.15
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
Track-Finder Test Plans
Approximate schedule
Jan.’03: SP prototype completed, initial tests begin
Î Feb.’03: MPC→SP optical link tests
Î Mar.’03: SP trigger logic tests
Î Apr.’03: CSC system tests with cosmic rays
Î May’03: beam tests with CSC chambers at CERN
Î
Time is very tight, and still have a lot of firmware and
software to write
Software will be written using XDAQ, hopefully in a way that
is relevant for future slice tests of muon system
Î
CMS Week, 3 Dec 2002
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D.Acosta, University of Florida
Software and Test Plans
Getting started on implementing a XDAQ compliant set
of software to run CSC trigger tests
VME (HAL):
Classes exist for VME configuration of TMB, MPC, CCB, and
TTC from Rice University.
Î Developing similar SP class with additional capability to
download LUTs and FPGAs from external files
‡ Integrating previous code from prototype tests in 2000
Î
Front-End Drivers (XDAQApp)
Developing “Driver” classes that instantiate VME classes
and execute XDAQWin configuration commands
Î
Bit3
DB
CMS Week, 3 Dec 2002
Track-Finder Crate
XDAQApplications:
SPDriver
CCBDriver
(MPCDriver)
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D.Acosta, University of Florida
CSC “TrigDAQ” Implementation
Track-Finder Crate
Peripheral Crate 1
Bit3
Bit3
DB
DB
DB
XDAQApplications:
MPCDriver
TMBDriver
CCBDriver
XDAQApplications:
SPDriver
CCBDriver
(MPCDriver)
“FEDs”
“FEDs”
DB
XDAQApplications:
EventGenerator/
Builder
XDAQ Win
“Run Control”
CMS Week, 3 Dec 2002
Peripheral Crate n
“Event Builder”
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D.Acosta, University of Florida